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I just finished a semester of VLSI Design at Utah Valley University with textbook _CMOS VLSI Design: A Circuits and Systems Perspective_ by Neil Weste and David Harris. On page 462 of that book, Weste and/or Harris say that if I need to find out if the integer A represented by a series of N bits is less than the integer B, also represented by a series of N bits, then I should just subtract A from B and see if there's a carry out. Subtracting A from B involves flipping the bits in A to get A', and adding A' and a single one to B. Page 449 of that same book indicates that the fastest way to add A' to B takes time t_pg + log_2( N) * t_AO + t_xor where (t_pg) is identified as the delay of a one-bit propagate/generate gate, (t_AO) is identified as the delay of an AND-OR gate, and (t_xor) is the delay of an XOR gate. Clearly (t_AO) is the bottleneck. So I want to ask a question about the following Verilog code.
Will a standard tool that implements this code end up building a circuit to create A' by flipping the bits in A, and build an adder to add A' to B?
Some graduate students I knew at the University of Washington pointed me to another algorithm that I think runs faster. The bottleneck in this algorithm is log_2( N) times the time it takes to execute a NOR gate, a NAND gate, and a two-by-one multiplexer in parallel (in other words the time it takes to do the slowest of those three gates). This algorithm wouldn't involve the construction of an adder or a bit flipper at all. I've written a Java program that, given the integer (N), the number of bits each operand has, produces a Verilog file that implements this second algorithm. I made an attempt to write a Verilog file that uses (N) as a parameter, but I never succeeded in writing anything that ran on "www.edaplayground.com" without generating compilation error messages. Are there people on this forum who are willing to take a look at that Java code if I post it here, and give me pointers as to how I can implement it with a Verilog file that uses (N) as a parameter?
Code Verilog - [expand] 1 2 3 4 5 6 module LessThan ( output result , input [ N-1:0] opLeft , [ N-1:0] opRight); assign result = opLeft < opRight; endmodule
Will a standard tool that implements this code end up building a circuit to create A' by flipping the bits in A, and build an adder to add A' to B?
Some graduate students I knew at the University of Washington pointed me to another algorithm that I think runs faster. The bottleneck in this algorithm is log_2( N) times the time it takes to execute a NOR gate, a NAND gate, and a two-by-one multiplexer in parallel (in other words the time it takes to do the slowest of those three gates). This algorithm wouldn't involve the construction of an adder or a bit flipper at all. I've written a Java program that, given the integer (N), the number of bits each operand has, produces a Verilog file that implements this second algorithm. I made an attempt to write a Verilog file that uses (N) as a parameter, but I never succeeded in writing anything that ran on "www.edaplayground.com" without generating compilation error messages. Are there people on this forum who are willing to take a look at that Java code if I post it here, and give me pointers as to how I can implement it with a Verilog file that uses (N) as a parameter?
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