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[SOLVED] Trying to Use Verilog Parameters to Code my own Less Than

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kvnsmnsn

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I just finished a semester of VLSI Design at Utah Valley University with textbook _CMOS VLSI Design: A Circuits and Systems Perspective_ by Neil Weste and David Harris. On page 462 of that book, Weste and/or Harris say that if I need to find out if the integer A represented by a series of N bits is less than the integer B, also represented by a series of N bits, then I should just subtract A from B and see if there's a carry out. Subtracting A from B involves flipping the bits in A to get A', and adding A' and a single one to B. Page 449 of that same book indicates that the fastest way to add A' to B takes time t_pg + log_2( N) * t_AO + t_xor where (t_pg) is identified as the delay of a one-bit propagate/generate gate, (t_AO) is identified as the delay of an AND-OR gate, and (t_xor) is the delay of an XOR gate. Clearly (t_AO) is the bottleneck. So I want to ask a question about the following Verilog code.

Code Verilog - [expand]
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module LessThan ( output          result
                ,  input [ N-1:0] opLeft
                ,        [ N-1:0] opRight);
 
  assign result = opLeft < opRight;
endmodule


Will a standard tool that implements this code end up building a circuit to create A' by flipping the bits in A, and build an adder to add A' to B?

Some graduate students I knew at the University of Washington pointed me to another algorithm that I think runs faster. The bottleneck in this algorithm is log_2( N) times the time it takes to execute a NOR gate, a NAND gate, and a two-by-one multiplexer in parallel (in other words the time it takes to do the slowest of those three gates). This algorithm wouldn't involve the construction of an adder or a bit flipper at all. I've written a Java program that, given the integer (N), the number of bits each operand has, produces a Verilog file that implements this second algorithm. I made an attempt to write a Verilog file that uses (N) as a parameter, but I never succeeded in writing anything that ran on "www.edaplayground.com" without generating compilation error messages. Are there people on this forum who are willing to take a look at that Java code if I post it here, and give me pointers as to how I can implement it with a Verilog file that uses (N) as a parameter?
 
Last edited by a moderator:

Hi,

Definitely, on this forum, there are fewer people that understand Java than there are that understand English. Presenting a description in Java rather than a description in English limits your chances of getting help. Posting the verilog code you attempted, in addition, will help you realise where you made mistakes and will help improve your verilog skills overall.
 
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Reactions: andre_luis

    FvM

    Points: 2
    Helpful Answer Positive Rating
building a circuit
I guess you know about IC 7485 (4-bit magnitude comparator). Cascade additional IC's to cover any number of bits.

However it looks like your code segment starts with the MSB, correct? Compares bits one position at a time, until 'A' bit is different from 'B' bit. Immediately you can exit, bypassing less significant comparisons. That approach is suitable for lengthy integers. If you wish to compare speeds, you might find there's a breakeven value for N that lets the other algorithm take less time. (I don't know where that point is nor do I know Java or Verilog.)
 

Will a standard tool that implements this code end up building a circuit to create A' by flipping the bits in A, and build an adder to add A' to B?
Presume that recent FPGA implement fast carry chain in hardware, the answer is yes. Under circumstances, the synthesis tool might also make use of integer DSP blocks, if available.
 

Akanimo posted:
Posting the verilog code you attempted, in addition, will help you realise where you made mistakes and will help improve your verilog skills overall.
Here's the only version I could find of my attempt to write a LessThan module using Verilog parameters:
Code:
// (c) Kevin Simonson 2023

    ////////////////////////////////////////////////////////////////////////////
////// Module (lessThan), parameterized by (nmBits), takes as input two va-   //
// lues, (lssr) and (grtr), each (nmBits) bits long, and produces as output   //
// (result) which is just one bit. If the unsigned numeric value of (lssr) is //
// less than the unsigned numeric value of (grtr), then (result) is a logical //
// one; otherwise, (result) is a logical zero. This module is designed to     //
// take roughly the same time to calculate its result for one pair of values  //
// as it does for any other pair of values. ////////////////////////////////////
//////////////////////////////////////////////
module LessThan #( nmBits = 2)
                ( result, lssr, grtr);
  // (result) is high if unsigned (lssr) is numerically less than unsigned
  // (grtr), and is low otherwise.
  localparam             maxBit   = nmBits - 1;
  output reg             result;
  input      [ maxBit:0] lssr;
  input      [ maxBit:0] grtr;

  localparam             ceiLog2  = $clog2( nmBits);
  localparam             limit    = 2 * nmBits - 1;
  localparam             recMax   = 5 * (3 * nmBits - ceiLog2 - 2);
  localparam             nbMinTwo = nmBits - 2;

  typedef integer rec_array [    recMax: 0     ];
  typedef integer nde_array [  nbMinTwo:-nmBits];
  typedef integer bse_array [ ceiLog2+1: 0     ];

  // Function (getRecipe) produces a list of operators with their arguments that
  // the code after the function uses to calculate whether (lssr) is less than
  // (grtr).

  function rec_array getRecipe ();
    // For any particular node (nd), (lssThn[ nd]) is high when the portion of
    // (lssr) under its subtree is less than the portion of (grtr) under the
    // same subtree, and low otherwise; while for (nd) at level (lvl) in the bi-
    // nary tree with (equ[ nd]) high, (eqty[ nd + maxBit - lvl]) is high if the
    // portion of (lssr) under its subtree is equal to the portion of (grtr) un-
    // der the same subtree, and low otherwise; and with (equ[ nd]) low,
    // (eqty[ nd + maxBit - lvl]) is high if the portion of (lssr) under that
    // subtree is unequal to the portion of (grtr) under that subtree. For each
    // level in the subtree, (eqty) doesn't have a value for the lowest index,
    // corresponding to each node (nd) where (ndEq[ nd]) is low, and (lssThn)
    // doesn't have values for level zero, except that (lssThn[ -1] is high if
    // the least significant bit of (lssr) is less than the least significant
    // bit of (grtr), and low otherwise. Wire arrays (lssThn) and (eqty) are de-
    // clared after this function. Array (res) is the recipe with operators and
    // arguments to the operators.
    automatic nde_array equ;
    automatic nde_array ndEq;
    automatic rec_array res;
    automatic integer   rBase = 0;
    // At any node (nd) in the binary tree, (level) is the level it is at, where
    // (ceiLog2) is the level of the tree's root, and zero is the level of the
    // leaves. (iLimit) is the number of nodes at any given level (ix) is the
    // index of the node (to be added to (bases[ level]) to get the index into
    // (lssThn) and (eqty). (lowLvl) is the level of that node's low child,
    // (lowIx) is the initial index of that child, (hghLvl) is the level of that
    // node's high child, and (hghIx) is the initial index of that child.
    automatic integer   level;
    automatic integer   iLimit;
    automatic integer   ix;
    automatic integer   lowLvl;
    automatic integer   lowIx;
    automatic integer   hghLvl;
    automatic integer   hghIx;
    // (node), (lowNode), and (hghNode) is the index used by (equ) and (ndEq)
    // for the node itself, its low child, and its high child, respectively. Any
    // path from the root to a leaf alternates values of (equ) along the way, so
    // if (equ[ nd]) is high, each of its children are low, and vice versa.
    // Therefore (flip) holds the negation of the value of (equ[ nd]). The value
    // of (eqty) for (nd)'s high child is used twice, once to determine
    // (lssThn[ nd]) and again to determine (eqty[ nd]), so I calculate its in-
    // dex into (eqty) once and stored it in (eqHgh), and then use that value
    // twice.
    automatic integer   node;
    automatic integer   lowNode;
    automatic integer   hghNode;
    automatic integer   flip;
    automatic integer   eqHgh;
    // First, initialize (bases) so that with a level (the level in the binary
    // tree) added to an index, the value to be indexed into (eqty) and (lssThn)
    // can be calculated.
    automatic bse_array bases;
    automatic integer   exp;
    automatic integer   nxPwr;
    automatic integer   pwr = 1;
    bases[ 0] = -nmBits;
    for (exp = 0; exp <= ceiLog2; exp = exp + 1)
    begin
      nxPwr           = 2 * pwr;
      bases[ exp + 1] = bases[ exp] + (limit + pwr) / nxPwr;
      pwr             = nxPwr;
    end
    // Initialize the values of (equ) and (ndEq) for the root node, and then
    // loop through each level of the binary tree, from the highest level to the
    // lowest level, and at each level loop through all nodes at that level.
    equ[  nbMinTwo] = 1;
    ndEq[ nbMinTwo] = 0;
    for (level = ceiLog2; 0 <= level; level = level - 1)
    begin
      iLimit = bases[ level + 1] - bases[ level];
      for (ix = 0; ix < iLimit; ix = ix + 1)
      begin
        node = bases[ level] + ix;
        if (level == 0)
        // Processing a leaf.
        begin
          if (ndEq[ node])
          begin
            res[ rBase    ] = equ[ node] ? 1 : 2;
            res[ rBase + 1] = ix - 1;
            res[ rBase + 2] = ix;
          end
          else
          begin
            res[ rBase    ] =  0;
            res[ rBase + 1] = -1;
            res[ rBase + 2] =  0;
          end
          rBase           = rBase + 5;
        end
        else
        // Processing an interior node.
        begin
          flip   = ! equ[ node];
          lowIx  = 2 * ix;
          lowLvl = level - 1;
          // While (hghIx) at level (hghLvl) is illegal (past the top of the bi-
          // nary tree), replace it with its low child, and decrement the level.
          hghIx = lowIx + 1;
          for (hghLvl = lowLvl; bases[ hghLvl + 1] <= bases[ hghLvl] + hghIx
                              ; hghLvl = hghLvl - 1)
            hghIx = 2 * hghIx;
          lowNode        = bases[ lowLvl] + lowIx;
          hghNode        = bases[ hghLvl] + hghIx;
          ndEq[ lowNode] = ndEq[ node];
          equ[  lowNode] = flip;
          ndEq[ hghNode] = 1;
          equ[  hghNode] = flip;
          eqHgh          = hghNode + maxBit - hghLvl;
          if      (0 < hghLvl)
          // Both children are interior nodes.
          begin
            if (level < ceiLog2)
            begin
              res[ rBase    ] =  7;
              res[ rBase + 1] = node;
              res[ rBase + 2] = eqHgh;
              res[ rBase + 3] = flip ? lowNode : hghNode;
              res[ rBase + 4] = flip ? hghNode : lowNode;
            end
            else
            begin
              res[ rBase    ] =  5;
              res[ rBase + 1] = eqHgh;
              res[ rBase + 2] = flip ? lowNode : hghNode;
              res[ rBase + 3] = flip ? hghNode : lowNode;
            end
          end
          else if (1 < level)
          // One child is an interior node and the other is a leaf.
          begin
            if (level < ceiLog2)
            begin
              if (flip)
              begin
                res[ rBase    ] =  8;
                res[ rBase + 3] = lowNode;
                res[ rBase + 4] = hghIx;
              end
              else
              begin
                res[ rBase    ] =  9;
                res[ rBase + 3] = hghIx;
                res[ rBase + 4] = lowNode;
              end
              res[ rBase + 1] = node;
              res[ rBase + 2] = eqHgh;
            end
            else
            begin
              res[ rBase    ] =  6;
              res[ rBase + 1] = eqHgh;
              res[ rBase + 2] = hghIx;
              res[ rBase + 3] = lowNode;
            end
          end
          else
          // Both children are leaves.
          begin
            if (level < ceiLog2)
            begin
              if      (-nmBits < lowNode)
              begin
                res[ rBase    ] = 10;
                res[ rBase + 3] = flip ? lowIx : hghIx;
                res[ rBase + 4] = flip ? hghIx : lowIx;
              end
              else if (flip)
              begin
                res[ rBase    ] =  8;
                res[ rBase + 3] = -1;
                res[ rBase + 4] = hghIx;
              end
              else
              begin
                res[ rBase    ] =  9;
                res[ rBase + 3] = hghIx;
                res[ rBase + 4] = -1;
              end
              res[ rBase + 1] = node;
              res[ rBase + 2] = eqHgh;
            end
            else
            begin
              res[ rBase    ] =  6;
              res[ rBase + 1] = eqHgh;
              res[ rBase + 2] =  1;
              res[ rBase + 3] = -1;
            end
          end
          rBase = rBase + 5;
          // For any interior node, check to see whether (eqty) needs to be cal-
          // culated.
          if (ndEq[ node])
          begin
            res[ rBase    ] = flip ? 3 : 4;
            res[ rBase + 1] = node + maxBit - level;
            res[ rBase + 2] = lowNode + maxBit - lowLvl;
            res[ rBase + 3] = eqHgh;
            rBase           = rBase + 5;
          end
        end
      end
    end
    return res;
  endfunction

  reg                  lssThn [        nmBits-3:-1];
  reg                  eqty   [ limit-ceiLog2-2: 0];
  localparam rec_array recipe = getRecipe();
  genvar               recBase;

  // For each operator in (recipe), execute its function on the arguments that
  // follow it in (recipe). The operators are sorted from least number of argu-
  // ments (2) to highest number of arguments (4).
  generate
    for (recBase = 0; recBase < recMax; recBase = recBase + 5)
    begin
      always_comb
      begin
        localparam ar_1 = recipe[ recBase + 1];
        localparam ar_2 = recipe[ recBase + 2];
        localparam ar_3 = recipe[ recBase + 3];
        localparam ar_4 = recipe[ recBase + 4];
        case (recipe[ recBase])
                0 : lssThn[ ar_1] = ~ (lssr[ ar_2] | ~ grtr[ ar_2]);
                1 : eqty[ ar_1]   = lssr[ ar_2] == grtr[ ar_2];
                2 : eqty[ ar_1]   = lssr[ ar_2] ^  grtr[ ar_2];
                3 : eqty[ ar_1]   = ~ (eqty[ ar_2] & eqty[ ar_3]);
                4 : eqty[ ar_1]   = ~ (eqty[ ar_2] | eqty[ ar_3]);
                5 : result        = eqty[ ar_1] ? lssThn[ ar_2] : lssThn[ ar_3];
                6 : result        = eqty[ ar_1] ?   grtr[ ar_2] : lssThn[ ar_3];
                7 : lssThn[ ar_1] = eqty[ ar_2] ? lssThn[ ar_3] : lssThn[ ar_4];
                8 : lssThn[ ar_1] = eqty[ ar_2] ? lssThn[ ar_3] :   grtr[ ar_4];
                9 : lssThn[ ar_1] = eqty[ ar_2] ?   grtr[ ar_3] : lssThn[ ar_4];
          default : lssThn[ ar_1] = eqty[ ar_2] ?   grtr[ ar_3] :   grtr[ ar_4];
        endcase
      end
    end
  endgenerate

endmodule

And here's the test file I used:

Code:
// (c) Kevin Simonson 2025

module t_LessThan;
  reg  [ 4:0] lssr;
  reg  [ 4:0] grtr;
  wire        lsTh;

  LessThan #( 5) lt5( lsTh, lssr, grtr);

  initial
  begin
       lssr = 5'b00000; grtr = 5'b00000;
    #3                  grtr = 5'b00001;
    #3 lssr = 5'b11110; grtr = 5'b11111;
    #3 lssr = 5'b11111;
  end

  always @( lssr, grtr, lsTh)
  begin
    $display
      ( "t: %2t, lssr: %5b, grtr: %5b, lsTh: %1b"
      , $time  , lssr     , grtr     , lsTh);
  end
endmodule

I started up "edaplayground.com", selected the Synopsys tool, ran it, and got the following three error messages and a boatload of warnings:

Code:
Error-[ICPD] Illegal combination of drivers
design.sv, 241
  Illegal combination of procedural drivers
  Variable "lssThn" is driven by an invalid combination of procedural drivers.
  Variables written on left-hand of "always_comb" cannot be written to by any 
  other processes, including other "always_comb" processes.
  This variable is declared at "design.sv", 241: reg lssThn[(nmBits - 
  3):(-1)];
  The first driver is at "design.sv", 252: always_comb  begin : 
  genblk1[30].unnamed$$_0
  
   ...
  The second driver is at "design.sv", 252: always_comb  begin : 
  genblk1[10].unnamed$$_0
  
   ...


Error-[ICPD] Illegal combination of drivers
design.sv, 241
  Illegal combination of procedural drivers
  Variable "lssThn" is driven by an invalid combination of procedural drivers.
  Variables written on left-hand of "always_comb" cannot be written to by any 
  other processes, including other "always_comb" processes.
  This variable is declared at "design.sv", 241: reg lssThn[(nmBits - 
  3):(-1)];
  The first driver is at "design.sv", 252: always_comb  begin : 
  genblk1[35].unnamed$$_0
  
   ...
  The second driver is at "design.sv", 252: always_comb  begin : 
  genblk1[15].unnamed$$_0
  
   ...


Error-[ICPD] Illegal combination of drivers
design.sv, 241
  Illegal combination of procedural drivers
  Variable "lssThn" is driven by an invalid combination of procedural drivers.
  Variables written on left-hand of "always_comb" cannot be written to by any 
  other processes, including other "always_comb" processes.
  This variable is declared at "design.sv", 241: reg lssThn[(nmBits - 
  3):(-1)];
  The first driver is at "design.sv", 252: always_comb  begin : 
  genblk1[40].unnamed$$_0
  
   ...
  The second driver is at "design.sv", 252: always_comb  begin : 
  genblk1[5].unnamed$$_0
  
   ...

55 warnings
3 errors
CPU time: .263 seconds to compile
Exit code expected: 0, received: 255
Done

Can anyone tell me what these error messages mean? And perhaps some pointers so that I can fix my Verilog code?
 

The Verilog I included in that last post might be a little difficult to understand, so I decided I'd include the following chart that explains my algorithm. It begins with a demo for the number of bits (N) equaling 23, but there follows a few diagrams that show the general algorithm. If there are (N) bits in each of (A) and (B), then the circuit becomes a binary tree, with the (Alt) value at the root high if (A) is less than (B) and low otherwise. If you have any questions about this chart, be sure to let me know, and I'll answer the best I can.
Code:
Leaves                                                           Root
,----------------------------------------------------------------------.
| a22 ?= b22                    | a22:20 == b22:20   | a22:16 |        |
|-------------------------------|                    | ==     |        |
| a21 ?= b21 | a21:20 == b21:20 | a22:20 != b22:20   | b22:16 |        |
|------------| a21:20 != b21:20 |                    |        |        |
| a20 ?= b20 | a21:20 >* b21:20 | a22:20 <* b22:20   | a22:16 |        |
|------------+------------------+--------------------| !=     |        |
| a19 ?= b19 | a19:18 == b19:18 |                    | b22:16 |        |
|------------| a19:18 != b19:18 | a19:16 == b19:16   |        |        |
| a18 ?= b18 | a19:18 >* b19:18 |                    | a22:16 |        |
|------------+------------------| a19:16 != b19:16   | >*     |        |
| a17 ?= b17 | a17:16 == b17:16 |                    | b22:16 |        |
|------------| a17:16 != b17:16 | a19:16 <* b19:16   |        |        |
| a16 ?= b16 | a17:16 >* b17:16 |                    |        | a22:00 |
|------------+------------------+--------------------+--------| <      |
| a15 ?= b15 | a15:14 == b15:14 |    a15:12 |        |        | b22:00 |
|------------| a15:14 != b15:14 | == b15:12 |        |        |        |
| a14 ?= b14 | a15:14 <* b15:14 |    a15:12 | a15:08 |        |        |
|------------+------------------| != b15:12 | ==     |        |        |
| a13 ?= b13 | a13:12 == b13:12 |    a15:12 | b15:08 |        |        |
|------------| a13:12 != b13:12 | >* b15:12 |        |        |        |
| a12 ?= b12 | a13:12 <* b13:12 |           | a15:08 |        |        |
|------------+------------------+-----------| !=     |        |        |
| a11 ?= b11 | a11:10 == b11:10 |    a11:08 | b15:08 |        |        |
|------------| a11:10 != b11:10 | == b11:08 |        |        |        |
| a10 ?= b10 | a11:10 <* b11:10 |    a11:08 | a15:08 |        |        |
|------------+------------------| != b11:08 | <*     |        |        |
| a09 ?= b09 | a09:08 == b09:08 |    a11:08 | b15:08 |        |        |
|------------| a09:08 != b09:08 | >* b11:08 |        |        |        |
| a08 ?= b08 | a09:08 <* b09:08 |           |        | a15:00 |        |
|------------+------------------+-----------+--------| >=     |        |
| a07 ?= b07 | a07:06 == b07:06 |    a07:04 |        | b15:00 |        |
|------------| a07:06 != b07:06 | == b07:04 |        |        |        |
| a06 ?= b06 | a07:06 <* b07:06 |    a07:04 |        |        |        |
|------------+------------------| != b07:04 |        |        |        |
| a05 ?= b05 | a05:04 == b05:04 |    a07:04 |        |        |        |
|------------| a05:04 != b05:04 | >* b07:04 |        |        |        |
| a04 ?= b04 | a05:04 <* b05:04 |           | a07:00 |        |        |
|------------+------------------+-----------| <      |        |        |
| a03 ?= b03 | a03:02 == b03:02 |           | b07:00 |        |        |
|------------| a03:02 != b03:02 |           |        |        |        |
| a02 ?= b02 | a03:02 <* b03:02 |    a03:00 |        |        |        |
|------------+------------------| >= b03:00 |        |        |        |
| a01 ?= b01 |                  |           |        |        |        |
|------------| a01:00 <  b01:00 |           |        |        |        |
| a00 >= b00 |                  |           |        |        |        |
`----------------------------------------------------------------------'

?= checks for both equality and inequality
<* means less than unless they're equal; if they're equal it guarantees nothing
>* means greater than unless they're equal; if equal it guarantees nothing

If (Dn)'s range's low end not zero:
,---------------------------------------------.
| Up     |                                    |
|    Alt |                                    |
|    Equ | Alt := (Up.Equ ? Dn.Alt : Up.Alt)' |
|    Neq |                                    |
|--------| Equ := Up.Neq NOR Dn.Neq           |
| Dn     |                                    |
|    Alt | Neq := Up.Equ NAND Dn.Equ          |
|    Equ |                                    |
|    Neq |                                    |
`---------------------------------------------'

If (Dn)'s range's low end zero:
,---------------------------------------------.
| Up     |                                    |
|    Alt |                                    |
|    Equ |                                    |
|    Neq |                                    |
|--------| Alt := (Up.Equ ? Dn.Alt : Up.Alt)' |
| Dn     |                                    |
|    Alt |                                    |
|        |                                    |
|        |                                    |
`---------------------------------------------'

 Leaf | even distance from top         | odd distance from top
------+--------------------------------+--------------------------------
      | ,---------------------------.  | ,---------------------------.
      | | Alt := B[ k]              |  | | Alt := A[ k]              |
      | | Equ                       |  | | Equ                       |
      | |   :=      (        A[ k]  |  | |   :=      (        A[ k]  |
      | |           NAND     B[ k]) |  | |           NAND     B[ k]) |
      | |      NAND (    NOT A[ k]  |  | |      NAND (    NOT A[ k]  |
0 < k | |           NAND NOT B[ k]) |  | |           NAND NOT B[ k]) |
      | | Neq                       |  | | Neq                       |
      | |   :=      (        A[ k]  |  | |   :=      (        A[ k]  |
      | |           NAND NOT B[ k]) |  | |           NAND NOT B[ k]) |
      | |      NAND (    NOT A[ k]  |  | |      NAND (    NOT A[ k]  |
      | |           NAND     B[ k]) |  | |           NAND     B[ k]) |
      | `---------------------------'  | `---------------------------'
------+--------------------------------+--------------------------------
      | ,----------------------------. | ,-----------------------------.
  0   | | Alt := A[ 0] NOR NOT B[ 0] | | | Alt := NOT A[ 0] NAND B[ 0] |
      | `----------------------------' | `-----------------------------'

A < B === Root.Alt
Note that although (Neq) at one level does not appear to get used to calculate (Alt) at a higher level, it actually does, because it's used in the circuit for the multiplexer.
 
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Actually, your errors messages are referring to a SystemVerilog file, Design.sv. It is basically saying you're driving some signals with multiple drivers (from different processes). VHDL is my strength.
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Just check out the code lines mentioned to confirm this.
 
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Actually, your errors messages are referring to a SystemVerilog file, Design.sv. It is basically saying you're driving some signals with multiple drivers (from different processes).
But each of the three messages say that the multiple drivers are at line 252 and line 252. How can they be multiple drivers if the two drivers are the same driver? 252 and 252 are the same number, the same line.
 

What's genblk1[5].unnamed$$_0? And then there's [10], [30], [15], [35] and [40].
 

But each of the three messages say that the multiple drivers are at line 252 and line 252. How can they be multiple drivers if the two drivers are the same driver? 252 and 252 are the same number, the same line.
Due to generate construct, the variables are driven multiple times.
 

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