[SOLVED] Trying to Figure Out how to Test for Timing

[kvnsmnsn]

I've got a piece of Verilog that calculates (aOp*bOp+cOp):

module Tf ( output rslt
          ,  input aOp
          ,        bOp
          ,        cOp);
  supply0 ground;
  supply1 power;
  wire    a_b;
  wire    ab_c;

  nmos na( a_b , ground, aOp);
  nmos nb( rslt, a_b   , bOp);
  nmos nc( rslt, ground, cOp);
  pmos pa( ab_c, power , aOp);
  pmos pb( ab_c, power , bOp);
  pmos pc( rslt, ab_c  , cOp);
endmodule

How do I check for timing, assuming that the delay of each nmos is 2 time units and the delay for each pmos is 2 time units? I tried writing:

  #2 nmos na( a_b , ground, aOp);
  #2 nmos nb( rslt, a_b   , bOp);
  #2 nmos nc( rslt, ground, cOp);
  #2 pmos pa( ab_c, power , aOp);
  #2 pmos pb( ab_c, power , bOp);
  #2 pmos pc( rslt, ab_c  , cOp);

but the compiler doesn't like that. My test code is:

// (c) Kevin Simonson 2025

module t_Tf;
  reg  aOp;
  reg  bOp;
  reg  cOp;
  wire rslt;

  Tf f( rslt, aOp, bOp, cOp);

  initial
  begin
        aOp = 1'b0; bOp = 1'b0; cOp = 1'b0;
    #10                         cOp = 1'b1;
    #10             bOp = 1'b1; cOp = 1'b0;
    #10                         cOp = 1'b1;
    #10 aOp = 1'b1; bOp = 1'b0; cOp = 1'b0;
    #10                         cOp = 1'b1;
    #10             bOp = 1'b1; cOp = 1'b0;
    #10                         cOp = 1'b1;
    #10 $finish;
  end

  always @( aOp, bOp, cOp, rslt)
  begin
    $display
      ( "t: %2t, aOp: %1b, bOp: %1b, cOp: %1b"
      , $time  , aOp     , bOp     , cOp);
  end
endmodule

I'd just like to figure out how I can test the timing on this.

--- Updated Feb 28, 2025 ---

I've got a piece of Verilog that calculates (aOp*bOp+cOp):

module Tf ( output rslt
          ,  input aOp
          ,        bOp
          ,        cOp);
  supply0 ground;
  supply1 power;
  wire    a_b;
  wire    ab_c;

  nmos na( a_b , ground, aOp);
  nmos nb( rslt, a_b   , bOp);
  nmos nc( rslt, ground, cOp);
  pmos pa( ab_c, power , aOp);
  pmos pb( ab_c, power , bOp);
  pmos pc( rslt, ab_c  , cOp);
endmodule

How do I check for timing, assuming that the delay of each nmos is 2 time units and the delay for each pmos is 2 time units? I tried writing:

  #2 nmos na( a_b , ground, aOp);
  #2 nmos nb( rslt, a_b   , bOp);
  #2 nmos nc( rslt, ground, cOp);
  #2 pmos pa( ab_c, power , aOp);
  #2 pmos pb( ab_c, power , bOp);
  #2 pmos pc( rslt, ab_c  , cOp);

but the compiler doesn't like that. My test code is:

// (c) Kevin Simonson 2025

module t_Tf;
  reg  aOp;
  reg  bOp;
  reg  cOp;
  wire rslt;

  Tf f( rslt, aOp, bOp, cOp);

  initial
  begin
        aOp = 1'b0; bOp = 1'b0; cOp = 1'b0;
    #10                         cOp = 1'b1;
    #10             bOp = 1'b1; cOp = 1'b0;
    #10                         cOp = 1'b1;
    #10 aOp = 1'b1; bOp = 1'b0; cOp = 1'b0;
    #10                         cOp = 1'b1;
    #10             bOp = 1'b1; cOp = 1'b0;
    #10                         cOp = 1'b1;
    #10 $finish;
  end

  always @( aOp, bOp, cOp, rslt)
  begin
    $display
      ( "t: %2t, aOp: %1b, bOp: %1b, cOp: %1b"
      , $time  , aOp     , bOp     , cOp);
  end
endmodule

I'd just like to figure out how I can test the timing on this.

Oops! I meant it calculates ((aOp*bOp+cOp)'), and the test code is actually:

// (c) Kevin Simonson 2025

module t_Tf;
  reg  aOp;
  reg  bOp;
  reg  cOp;
  wire rslt;

  Tf f( rslt, aOp, bOp, cOp);

  initial
  begin
        aOp = 1'b0; bOp = 1'b0; cOp = 1'b0;
    #10                         cOp = 1'b1;
    #10             bOp = 1'b1; cOp = 1'b0;
    #10                         cOp = 1'b1;
    #10 aOp = 1'b1; bOp = 1'b0; cOp = 1'b0;
    #10                         cOp = 1'b1;
    #10             bOp = 1'b1; cOp = 1'b0;
    #10                         cOp = 1'b1;
    #10 $finish;
  end

  always @( aOp, bOp, cOp, rslt)
  begin
    $display
      ( "t: %2t, aOp: %1b, bOp: %1b, cOp: %1b, rslt: %1b"
      , $time  , aOp     , bOp     , cOp     , rslt);
  end
endmodule

Sorry for the typos!

 

[kvnsmnsn]

I did some experimenting with my code and came up with:

module Tf ( output rslt
          ,  input aOp
          ,        bOp
          ,        cOp);
  supply0 ground;
  supply1 power;
  wire    a_b;
  wire    ab_c;

  nmos #2 na( a_b , ground, aOp);
  nmos #2 nb( rslt, a_b   , bOp);
  nmos #2 nc( rslt, ground, cOp);
  pmos #2 pa( ab_c, power , aOp);
  pmos #2 pb( ab_c, power , bOp);
  pmos #2 pc( rslt, ab_c  , cOp);
endmodule

This worked just fine so it would appear that my problem is fixed.