E-goe
Member level 5
Hi,
Let me first describe my testsetup ( see attachment ).
The testsetup to debug the LVDS link between the sensor and the controller board contains 3 boards:
1.Digital controller board: this board contains an FPGA ( Spartan 3E ). This FPGA sends commands (CMOS levels )to the sensor, which is located on the plugin board. The data send back from the sensor to the controller obeys the LVDS electrical levels i.e common mode voltage of 1.25V and differential voltage of around 350mV.
2. The analog board: Board with some extra componenets on it ( ex. power supply's for the the sensor is on this board, ADC to perform others tests... )
Basically this board transfers the signals from the digital controller board to the plugin board ( which contains the sensor ) and visa versa.
3. The plugin board contains the sensor.
The sensor sends has 2 LVDS channels on it. One for the clock and one data channel. So a clock and data is send to the digital controller board.
This 3 board are stacked on each other through connectors.
So at last my question:
For the moment I am debugging the LVDS link have some troubles to get the LVDs link up and running. The bitrate is 200Mbps ( so not a very high bitrate LVDS channel).
If I measure the differential clock signal at the termination impedance of 100 Ohm at the digital controller board with a differential probe the signql looks oke. But when I measure the same signal at the plugin board I don't see this signal...
How can that be. Does someone has an explanation for this strange phenomena?
Reflections?????
The same apply's for the LVDS data channel....
I am measuring the signals with a differential probe and the bandwith of the digital scope is 1GHz.
Also when I send 0101010.... ( LVDS testpatten ) on the LVDS datachannel I measure an LVDS compatible signal on digital board. But when I send random pattgerns over the datalink the LVDS data output channel is severly corrupted. It doesn't even looks as an LVDS signal anymore.
Any comments?
Thanks
E-goe
Let me first describe my testsetup ( see attachment ).
The testsetup to debug the LVDS link between the sensor and the controller board contains 3 boards:
1.Digital controller board: this board contains an FPGA ( Spartan 3E ). This FPGA sends commands (CMOS levels )to the sensor, which is located on the plugin board. The data send back from the sensor to the controller obeys the LVDS electrical levels i.e common mode voltage of 1.25V and differential voltage of around 350mV.
2. The analog board: Board with some extra componenets on it ( ex. power supply's for the the sensor is on this board, ADC to perform others tests... )
Basically this board transfers the signals from the digital controller board to the plugin board ( which contains the sensor ) and visa versa.
3. The plugin board contains the sensor.
The sensor sends has 2 LVDS channels on it. One for the clock and one data channel. So a clock and data is send to the digital controller board.
This 3 board are stacked on each other through connectors.
So at last my question:
For the moment I am debugging the LVDS link have some troubles to get the LVDs link up and running. The bitrate is 200Mbps ( so not a very high bitrate LVDS channel).
If I measure the differential clock signal at the termination impedance of 100 Ohm at the digital controller board with a differential probe the signql looks oke. But when I measure the same signal at the plugin board I don't see this signal...
How can that be. Does someone has an explanation for this strange phenomena?
Reflections?????
The same apply's for the LVDS data channel....
I am measuring the signals with a differential probe and the bandwith of the digital scope is 1GHz.
Also when I send 0101010.... ( LVDS testpatten ) on the LVDS datachannel I measure an LVDS compatible signal on digital board. But when I send random pattgerns over the datalink the LVDS data output channel is severly corrupted. It doesn't even looks as an LVDS signal anymore.
Any comments?
Thanks
E-goe