UB18
Newbie level 4
- Joined
- Feb 7, 2013
- Messages
- 5
- Helped
- 0
- Reputation
- 0
- Reaction score
- 0
- Trophy points
- 1,281
- Activity points
- 1,311
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:40:38 02/07/2013
// Design Name:
// Module Name: mouse
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module MouseReceiver(
//Standard Inputs
input RESET,
input CLK,
//Mouse IO - CLK
input CLK_MOUSE_IN,
//Mouse IO - DATA
input DATA_MOUSE_IN,
//Control
input READ_ENABLE,
output [7:0] BYTE_READ,
output [1:0] BYTE_ERROR_CODE,
output BYTE_READY
);
//////////////////////////////////////////////////////////
// Clk Mouse delayed to detect clock edges
reg ClkMouseInDly;
always@(posedge CLK)
ClkMouseInDly <= CLK_MOUSE_IN;
//////////////////////////////////////////////////////////
//A simple state machine to handle the incoming 11-bit codewords
reg [2:0] Curr_State, Next_State;
reg [7:0] Curr_MSCodeShiftReg, Next_MSCodeShiftReg;
reg [3:0] Curr_BitCounter, Next_BitCounter;
reg Curr_ByteReceived, Next_ByteReceived;
reg [1:0] Curr_MSCodeStatus, Next_MSCodeStatus;
reg [15:0] Curr_TimeoutCounter, Next_TimeoutCounter;
//Sequential
always@(posedge CLK) begin
if(RESET) begin
Curr_State <= 3'b000;
Curr_MSCodeShiftReg <= 8'h00;
Curr_BitCounter <= 0;
Curr_ByteReceived <= 1'b0;
Curr_MSCodeStatus <= 2'b00;
Curr_TimeoutCounter <= 0;
end else begin
Curr_State <= Next_State;
Curr_MSCodeShiftReg <= Next_MSCodeShiftReg;
Curr_BitCounter <= Next_BitCounter;
Curr_ByteReceived <= Next_ByteReceived;
Curr_MSCodeStatus <= Next_MSCodeStatus;
Curr_TimeoutCounter <= Next_TimeoutCounter;
end
end
//Combinatorial
always@* begin
//defaults to make the State Machine more readable
Next_State = Curr_State;
Next_MSCodeShiftReg = Curr_MSCodeShiftReg;
Next_BitCounter = Curr_BitCounter;
Next_ByteReceived = 1'b0;
Next_MSCodeStatus = Curr_MSCodeStatus;
Next_TimeoutCounter = Curr_TimeoutCounter + 1'b1;
//The states
case (Curr_State)
3'b000: begin
//Falling edge of Mouse clock and MouseData is low i.e. start bit
if(READ_ENABLE & ClkMouseInDly & ~CLK_MOUSE_IN & ~DATA_MOUSE_IN) begin
Next_State = 3'b001;
Next_MSCodeStatus = 2'b00;
end
Next_BitCounter = 0;
end
// Read successive byte bits from the mouse here
3'b001: begin
if(Curr_TimeoutCounter == 50000) // 1ms timeout
Next_State = 3'b000;
else if(Curr_BitCounter == 8) begin // if last bit go to parity bit check
Next_State = 3'b010;
Next_BitCounter = 0;
end else if(ClkMouseInDly & ~CLK_MOUSE_IN) begin //Shift Byte bits in
Next_MSCodeShiftReg[6:0] = Curr_MSCodeShiftReg[7:1];
Next_MSCodeShiftReg[7] = DATA_MOUSE_IN;
Next_BitCounter = Curr_BitCounter + 1;
Next_TimeoutCounter = 0;
end
end
//Check Parity Bit
3'b010: begin
//Falling edge of Mouse clock and MouseData is odd parity
if(Curr_TimeoutCounter == 50000)
Next_State = 3'b000;
else if(ClkMouseInDly & ~CLK_MOUSE_IN) begin
if (DATA_MOUSE_IN != ~^Curr_MSCodeShiftReg[7:0]) // Parity bit error
Next_MSCodeStatus[0] = 1'b1;
Next_BitCounter = 0;
Next_State = 3'b011;
Next_TimeoutCounter = 0;
end
end
3'b011: begin
if(Curr_TimeoutCounter == 50000)
Next_State = 3'b000;
else if(ClkMouseInDly & ~CLK_MOUSE_IN) begin
Next_MSCodeStatus[1] = ~DATA_MOUSE_IN;
Next_BitCounter = 0;
Next_State = 3'b100;
Next_TimeoutCounter = 0;
end
end
//Final state
3'b100: begin
if(Curr_TimeoutCounter == 50000)
Next_State = 3'b000;
else if(CLK_MOUSE_IN & DATA_MOUSE_IN) begin
Next_ByteReceived = 1'b1;
Next_State = 3'b000;
end
end
//Default state
default: begin
Next_State = 3'b000;
Next_MSCodeShiftReg = 8'h00;
Next_BitCounter = 0;
Next_ByteReceived = 1'b0;
Next_MSCodeStatus = 2'b00;
Next_TimeoutCounter = 0;
end
endcase
end
assign BYTE_READY = Curr_ByteReceived;
assign BYTE_READ = Curr_MSCodeShiftReg;
assign BYTE_ERROR_CODE = Curr_MSCodeStatus;
endmodule
//TRANSMITTER
module MouseTransmitter(
//Standard Inputs
input RESET,
input CLK,
//Mouse IO - CLK
input CLK_MOUSE_IN,
output CLK_MOUSE_OUT_EN, // Allows for the control of the Clock line
//Mouse IO - DATA
input DATA_MOUSE_IN,
output DATA_MOUSE_OUT,
output DATA_MOUSE_OUT_EN,
//Control
input SEND_BYTE,
input [7:0] BYTE_TO_SEND,
output BYTE_SENT
);
//////////////////////////////////////////////////////////
// Clk Mouse delayed to detect clock edges
reg ClkMouseInDly;
always@(posedge CLK)
ClkMouseInDly <= CLK_MOUSE_IN;
//////////////////////////////////////////////////////////
//Now a state machine to control the flow of write data
reg [3:0] Curr_State, Next_State;
reg Curr_MouseClkOutWE, Next_MouseClkOutWE;
reg Curr_MouseDataOut, Next_MouseDataOut;
reg Curr_MouseDataOutWE, Next_MouseDataOutWE;
reg [15:0] Curr_SendCounter, Next_SendCounter;
reg Curr_ByteSent, Next_ByteSent;
reg [7:0] Curr_ByteToSend, Next_ByteToSend;
//Sequential
always@(posedge CLK) begin
if(RESET) begin
Curr_State <= 4'h0;
Curr_MouseClkOutWE <= 1'b0;
Curr_MouseDataOut <= 1'b0;
Curr_MouseDataOutWE <= 1'b0;
Curr_SendCounter <= 0;
Curr_ByteSent <= 1'b0;
Curr_ByteToSend <= 0;
end else begin
Curr_State <= Next_State;
Curr_MouseClkOutWE <= Next_MouseClkOutWE;
Curr_MouseDataOut <= Next_MouseDataOut;
Curr_MouseDataOutWE <= Next_MouseDataOutWE;
Curr_SendCounter <= Next_SendCounter;
Curr_ByteSent <= Next_ByteSent;
Curr_ByteToSend <= Next_ByteToSend;
end
end
//Combinatorial
always@* begin
//default values
Next_State = Curr_State;
Next_MouseClkOutWE = 1'b0;
Next_MouseDataOut = 1'b0;
Next_MouseDataOutWE = Curr_MouseDataOutWE;
Next_SendCounter = Curr_SendCounter;
Next_ByteSent = 1'b0;
Next_ByteToSend = Curr_ByteToSend;
case(Curr_State)
//IDLE
4'h0 : begin
if(SEND_BYTE) begin
Next_State = 4'h1;
Next_ByteToSend = BYTE_TO_SEND;
end
Next_MouseDataOutWE = 1'b0;
end
//Bring Clock line low for at least 100 microsecs i.e. 5000 clock cycles @ 50MHz
4'h1 : begin
if(Curr_SendCounter == 6000) begin
Next_State = 4'h2;
Next_SendCounter = 0;
end else
Next_SendCounter = Curr_SendCounter + 1'b1;
Next_MouseClkOutWE = 1'b1;
end
//Bring the Data Line Low and release the Clock line
4'h2 : begin
Next_State = 4'h3;
Next_MouseDataOutWE = 1'b1;
end
//Start Sending
4'h3 : begin // change data at falling edge of clock, start bit = 0
if(ClkMouseInDly & ~CLK_MOUSE_IN)
Next_State = 4'h4;
end
//Send Bits 0 to 7 - We need to send the byte
4'h4 : begin // change data at falling edge of clock
if(ClkMouseInDly & ~CLK_MOUSE_IN) begin
if(Curr_SendCounter == 7) begin
Next_State = 4'h5;
Next_SendCounter = 0;
end else
Next_SendCounter = Curr_SendCounter + 1'b1;
end
Next_MouseDataOut = Curr_ByteToSend[Curr_SendCounter];
end
//Send the parity bit
4'h5 : begin // change data at falling edge of clock
if(ClkMouseInDly & ~CLK_MOUSE_IN)
Next_State = 4'h6;
Next_MouseDataOut = ~^Curr_ByteToSend[7:0];
end
//Release Data line
4'h6 : begin
Next_State = 4'h7;
Next_MouseDataOutWE = 1'b0;
end
//Bring data line low
4'h7: begin
if(~DATA_MOUSE_IN)
Next_State = 4'h8;
end
//Bring clock line low
4'h8: begin
if(ClkMouseInDly & ~CLK_MOUSE_IN)
Next_State = 4'h9;
end
//Release data and clock
4'h9: begin
if(DATA_MOUSE_IN & CLK_MOUSE_IN)begin
Next_ByteSent = 1'b1;
Next_State = 4'h0;
end
end
endcase
end
///////////////////////////////////////////////////////////////
//Assign OUTPUTs
//Mouse IO - CLK
assign CLK_MOUSE_OUT_EN = Curr_MouseClkOutWE;
//Mouse IO - DATA
assign DATA_MOUSE_OUT = Curr_MouseDataOut;
assign DATA_MOUSE_OUT_EN = Curr_MouseDataOutWE;
//Control
assign BYTE_SENT = Curr_ByteSent;
endmodule
//Master State Machine module.
module MouseMasterSM(
input CLK,
input RESET,
//Transmitter Control
output SEND_BYTE,
output [7:0] BYTE_TO_SEND,
input BYTE_SENT,
//Receiver Control
output READ_ENABLE,
input [7:0] BYTE_READ,
input [1:0] BYTE_ERROR_CODE,
input BYTE_READY,
//Data Registers
output [7:0] MOUSE_DX,
output [7:0] MOUSE_DY,
output [7:0] MOUSE_STATUS,
output SEND_INTERRUPT
);
//////////////////////////////////////////////////////////////
// Main state machine - There is a setup sequence
//
// 1) Send FF -- Reset command,
// 2) Read FA -- Mouse Acknowledge,
// 2) Read AA -- Self-Test Pass
// 3) Read 00 -- Mouse ID
// 4) Send F4 -- Start transmitting command,
// 5) Read FA -- Mouse Acknowledge,
//
// If at any time this chain is broken, the SM will restart from
// the beginning. Once it has finished the set-up sequence, the read enable flag
// is raised.
// The host is then ready to read mouse information 3 bytes at a time:
// S1) Wait for first read, When it arrives, save it to Status. Goto S2.
// S2) Wait for second read, When it arrives, save it to DX. Goto S3.
// S3) Wait for third read, When it arrives, save it to DY. Goto S1.
// Send interrupt.
//State Control
reg [3:0] Curr_State, Next_State;
reg [23:0] Curr_Counter, Next_Counter;
//Transmitter Control
reg Curr_SendByte, Next_SendByte;
reg [7:0] Curr_ByteToSend, Next_ByteToSend;
//Receiver Control
reg Curr_ReadEnable, Next_ReadEnable;
//Data Registers
reg [7:0] Curr_Status, Next_Status;
reg [7:0] Curr_Dx, Next_Dx;
reg [7:0] Curr_Dy, Next_Dy;
reg Curr_SendInterrupt, Next_SendInterrupt;
//Sequential
always@(posedge CLK) begin
if(RESET) begin
Curr_State <= 4'h0;
Curr_Counter <= 0;
Curr_SendByte <= 1'b0;
Curr_ByteToSend <= 8'h00;
Curr_ReadEnable <= 1'b0;
Curr_Status <= 8'h00;
Curr_Dx <= 8'h00;
Curr_Dy <= 8'h00;
Curr_SendInterrupt <= 1'b0;
end else begin
Curr_State <= Next_State;
Curr_Counter <= Next_Counter;
Curr_SendByte <= Next_SendByte;
Curr_ByteToSend <= Next_ByteToSend;
Curr_ReadEnable <= Next_ReadEnable;
Curr_Status <= Next_Status;
Curr_Dx <= Next_Dx;
Curr_Dy <= Next_Dy;
Curr_SendInterrupt <= Next_SendInterrupt;
end
end
//Combinatorial
always@* begin
Next_State = Curr_State;
Next_Counter = Curr_Counter;
Next_SendByte = 1'b0;
Next_ByteToSend = Curr_ByteToSend;
Next_ReadEnable = 1'b0;
Next_Status = Curr_Status;
Next_Dx = Curr_Dx;
Next_Dy = Curr_Dy;
Next_SendInterrupt = 1'b0;
case(Curr_State)
//Initialise State - Wait here for 10ms before trying to initialise the mouse.
4'h0: begin
if(Curr_Counter == 5000000) begin // 1/100th sec at 50MHz clock
Next_State = 4'h1;
Next_Counter = 0;
end else
Next_Counter = Curr_Counter + 1'b1;
end
//Start initialisation by sending FF
4'h1: begin
Next_State = 4'h2;
Next_SendByte = 1'b1;
Next_ByteToSend = 8'hFF;
end
//Wait for confirmation of the byte being sent
4'h2: begin
if(BYTE_SENT)
Next_State = 4'h3;
end
//Wait for confirmation of a byte being received
//If the byte is FA goto next state, else re-initialise.
4'h3: begin
if(BYTE_READY) begin
if((BYTE_READ == 8'hFA) & (BYTE_ERROR_CODE == 2'b00))
Next_State = 4'h4;
else
Next_State = 4'h0;
end
Next_ReadEnable = 1'b1;
end
//Wait for self-test pass confirmation
//If the byte received is AA goto next state, else re-initialise
4'h4: begin
if(BYTE_READY) begin
if((BYTE_READ == 8'hAA) & (BYTE_ERROR_CODE == 2'b00))
Next_State = 4'h5;
else
Next_State = 4'h0;
end
Next_ReadEnable = 1'b1;
end
//Wait for confirmation of a byte being received
//If the byte is 00 goto next state (MOUSE ID) else re-initialise
4'h5: begin
if(BYTE_READY) begin
if((BYTE_READ == 8'h00) & (BYTE_ERROR_CODE == 2'b00))
Next_State = 4'h6;
else
Next_State = 4'h0;
end
Next_ReadEnable = 1'b1;
end
//Send F4 - to start mouse transmit
4'h6: begin
Next_State = 4'h7;
Next_SendByte = 1'b1;
Next_ByteToSend = 8'hF4;
end
//Wait for confirmation of the byte being sent
4'h7: if(BYTE_SENT) Next_State = 4'h8;
//Wait for confirmation of a byte being received
//If the byte is FA goto next state, else re-initialise
4'h8: begin
if(BYTE_READY) begin
if((BYTE_READ == 8'hFA) & (BYTE_ERROR_CODE == 2'b00))
Next_State = 4'h9;
else
Next_State = 4'h0;
end
Next_ReadEnable = 1'b1;
end
///////////////////////////////////////////////////////////
//At this point the SM has initialised the mouse.
//Now we are constantly reading. If at any time
//there is an error, we will re-initialise
//the mouse - just in case. ///////////////////////////////////////////////////////////
//Wait for the confirmation of a byte being received.
//This byte will be the first of three, the status byte.
//If a byte arrives, but is corrupted, then we re-initialise
4'h9: begin
if(BYTE_READY & (BYTE_ERROR_CODE == 2'b00)) begin
Next_State = 4'hA;
Next_Status = BYTE_READ;
end else
Next_State = 4'h0;
Next_Counter = 0;
Next_ReadEnable = 1'b1;
end
//Wait for confirmation of a byte being received
//This byte will be the second of three, the Dx byte.
4'hA: begin
if(BYTE_READY & (BYTE_ERROR_CODE == 2'b00)) begin
Next_State = 4'hB;
Next_Dx = BYTE_READ;
end else
Next_State = 4'hA;
Next_ReadEnable = 1'b1;
end
//Wait for confirmation of a byte being received
//This byte will be the third of three, the Dy byte.
4'hB: begin
if(BYTE_READY & (BYTE_ERROR_CODE == 2'b00)) begin
Next_State = 4'hC;
Next_Dy = BYTE_READ;
end else
Next_State = 4'hB;
Next_ReadEnable = 1'b1;
end
//Send Interrupt State
4'hC: begin
Next_State = 4'h9;
Next_SendInterrupt = 1'b1;
end
//Default State
default: begin
Next_State = 4'h0;
Next_Counter = 0;
Next_SendByte = 1'b0;
Next_ByteToSend = 8'hFF;
Next_ReadEnable = 1'b0;
Next_Status = 8'h00;
Next_Dx = 8'h00;
Next_Dy = 8'h00;
Next_SendInterrupt = 1'b0;
end
endcase
end
///////////////////////////////////////////////////
//Tie the SM signals to the IO
//Transmitter
assign SEND_BYTE = Curr_SendByte;
assign BYTE_TO_SEND = Curr_ByteToSend;
//Receiver
assign READ_ENABLE = Curr_ReadEnable;
//Output Mouse Data
assign MOUSE_DX = Curr_Dx;
assign MOUSE_DY = Curr_Dy;
assign MOUSE_STATUS = Curr_Status;
assign SEND_INTERRUPT = Curr_SendInterrupt;
endmodule
//Mouse Transceiver
//Mouse transceiver
module MouseTransceiver(
//Standard Inputs
input RESET,
input CLK,
//IO - Mouse side
inout CLK_MOUSE,
inout DATA_MOUSE,
// Mouse data information
output [3:0] Mouse_SegSel,
output [6:0] Mouse_DispOut,
output [3:0] Mouse_Led
);
// X, Y Limits of Mouse Position e.g. VGA Screen with 160 x 120 resolution
parameter [7:0] MouseLimitX = 160;
parameter [7:0] MouseLimitY = 120;
// Mouse data information
reg [3:0] MouseStatus;
reg [7:0] MouseX;
reg [7:0] MouseY;
//TriState Signals
//Clk
reg ClkMouseIn;
wire ClkMouseOutEnTrans;
//Data
wire DataMouseIn;
wire DataMouseOutTrans;
wire DataMouseOutEnTrans;
//Clk Output - can be driven by host or device
assign CLK_MOUSE = ClkMouseOutEnTrans ? 1'b0 : 1'bz;
//Clk Input
assign DataMouseIn = DATA_MOUSE;
//Clk Output - can be driven by host or device
assign DATA_MOUSE = DataMouseOutEnTrans ? DataMouseOutTrans : 1'bz;
/////////////////////////////////////////////////////////////////////
//This section filters the incoming Mouse clock to make sure that
//it is stable before data is latched by either transmitter
//or receiver modules
reg [7:0] MouseClkFilter;
always@(posedge CLK) begin
if(RESET)
ClkMouseIn <= 1'b0;
else begin
//A simple shift register
MouseClkFilter[7:1] <= MouseClkFilter[6:0];
MouseClkFilter[0] <= CLK_MOUSE;
//falling edge
if(ClkMouseIn & (MouseClkFilter == 8'h00))
ClkMouseIn <= 1'b0;
//rising edge
else if(~ClkMouseIn & (MouseClkFilter == 8'hFF))
ClkMouseIn <= 1'b1;
end
end
///////////////////////////////////////////////////////
//Instantiate the Transmitter module
wire SendByteToMouse;
wire ByteSentToMouse;
wire [7:0] ByteToSendToMouse;
MouseTransmitter T(
//Standard Inputs
.RESET (RESET),
.CLK(CLK),
//Mouse IO - CLK
.CLK_MOUSE_IN(ClkMouseIn),
.CLK_MOUSE_OUT_EN(ClkMouseOutEnTrans),
//Mouse IO - DATA
.DATA_MOUSE_IN(DataMouseIn),
.DATA_MOUSE_OUT(DataMouseOutTrans),
.DATA_MOUSE_OUT_EN (DataMouseOutEnTrans),
//Control
.SEND_BYTE(SendByteToMouse),
.BYTE_TO_SEND(ByteToSendToMouse),
.BYTE_SENT(ByteSentToMouse)
);
///////////////////////////////////////////////////////
//Instantiate the Receiver module
wire ReadEnable;
wire [7:0] ByteRead;
wire [1:0] ByteErrorCode;
wire ByteReady;
MouseReceiver R(
//Standard Inputs
.RESET(RESET),
.CLK(CLK),
//Mouse IO - CLK
.CLK_MOUSE_IN(ClkMouseIn),
//Mouse IO - DATA
.DATA_MOUSE_IN(DataMouseIn),
//Control
.READ_ENABLE (ReadEnable),
.BYTE_READ(ByteRead),
.BYTE_ERROR_CODE(ByteErrorCode),
.BYTE_READY(ByteReady)
);
///////////////////////////////////////////////////////
//Instantiate the Master State Machine module
wire [7:0] MouseStatusRaw;
wire [7:0] MouseDxRaw;
wire [7:0] MouseDyRaw;
wire SendInterrupt;
MouseMasterSM MSM(
//Standard Inputs
.RESET(RESET),
.CLK(CLK),
//Transmitter Interface
.SEND_BYTE(SendByteToMouse),
.BYTE_TO_SEND(ByteToSendToMouse),
.BYTE_SENT(ByteSentToMouse),
//Receiver Interface
.READ_ENABLE (ReadEnable),
.BYTE_READ(ByteRead),
.BYTE_ERROR_CODE(ByteErrorCode),
.BYTE_READY(ByteReady),
//Data Registers
.MOUSE_STATUS(MouseStatusRaw),
.MOUSE_DX(MouseDxRaw),
.MOUSE_DY(MouseDyRaw),
.SEND_INTERRUPT(SendInterrupt)
);
//Pre-processing - handling of overflow and signs.
//More importantly, this keeps tabs on the actual X/Y
//location of the mouse.
wire signed [8:0] MouseDx;
wire signed [8:0] MouseDy;
wire signed [8:0] MouseNewX;
wire signed [8:0] MouseNewY;
//Wires for display display interface
wire [6:0] Disp_Out;
wire [3:0] SegSelect;
wire [3:0] LedDis;
//DX and DY are modified to take account of overflow and direction
assign MouseDx = (MouseStatusRaw[6]) ? (MouseStatusRaw[4] ? {MouseStatusRaw[4],8'h00} : {MouseStatusRaw[4],8'hFF} ) : {MouseStatusRaw[4],MouseDxRaw[7:0]};
assign MouseDy = (MouseStatusRaw[7]) ? (MouseStatusRaw[5] ? {MouseStatusRaw[5],8'h00} : {MouseStatusRaw[5],8'hFF} ) : {MouseStatusRaw[5],MouseDyRaw[7:0]};
// calculate new mouse position
assign MouseNewX = {1'b0,MouseX} + MouseDx;
assign MouseNewY = {1'b0,MouseY} + MouseDy;
always@(posedge CLK) begin
if(RESET) begin
MouseStatus <= 0;
MouseX <= MouseLimitX/2;
MouseY <= MouseLimitY/2;
end else if (SendInterrupt) begin
//Status is stripped of all unnecessary info
MouseStatus <= MouseStatusRaw[3:0];
//X is modified based on DX with limits on max and min
if(MouseNewX < 0)
MouseX <= 0;
else if(MouseNewX > (MouseLimitX-1))
MouseX <= MouseLimitX-1;
else
MouseX <= MouseNewX[7:0];
//Y is modified based on DY with limits on max and min
if(MouseNewY < 0)
MouseY <= 0;
else if(MouseNewY > (MouseLimitY-1))
MouseY <= MouseLimitY-1;
else
MouseY <= MouseNewY[7:0];
end
end
//in the end
//Display Interface
//Leds[3:0] display the status
//7-SegLed 0(LSB Nibble) and 1 display Mouse X Co ordinates
//7-SegLed 2(LSB Nibble) and 3 display Mouse Y Co ordinates
//1011 B 2nd Seg from left Basys Board (MSB Nibble) 1010 A 1st
//Seg from left Basys Board (LSB Nibble)
//1101 D 4th Seg from left Basys Board (MSB Nibble) 1100 C 3rd
//Seg from left Basys Board (LSB Nibble)
all_7_seg Sev_seg(
.CLK(CLK),
.MouseDX(MouseX),
.MouseDY(MouseY),
.MouseStats(MouseStatus),
.DispOut(Disp_Out),
.SEG_SELECT(SegSelect),
.Led_disp(LedDis)
);
assign Mouse_DispOut = Disp_Out;
assign Mouse_SegSel = SegSelect;
assign Mouse_Led = LedDis;
endmodule
//main module of seven seg
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 02:24:47 02/01/2013
// Design Name:
// Module Name: all_7_seg
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module all_7_seg(
input CLK,
input [7:0] MouseDX,
input [7:0] MouseDY,
input [3:0] MouseStats,
output [6:0] DispOut,
output [3:0] SEG_SELECT,
output [3:0] Led_disp
);
wire [6:0] Dispout_1;
wire [3:0] SEG_SELCET_1;
wire [1:0] Bit2Count;
wire [3:0] MuxOut;
GenericCounter Bit16(
.CLK(CLK),
.TRIGG_OUT(Bit16TrigOut)
);
GenericCounter2 Bit2(
.CLK(Bit16TrigOut),
.TRIGG_OUT(Bit2TrigOut),
.COUNT(Bit2Count)
);
reg [3:0] DECCOUNT_Disp0;
reg [3:0] DECCOUNT_Disp1;
reg [3:0] DECCOUNT_Disp2;
reg [3:0] DECCOUNT_Disp3;
reg [3:0] LED_DISP_1;
/*wires
wire [3:0] DECCOUNT0;
wire [3:0] DECCOUNT1;
wire [3:0] DECCOUNT2;
wire [3:0] DECCOUNT3;
*/
always@(CLK or MouseDY or MouseDX or MouseStats) begin
DECCOUNT_Disp0 <= MouseDY[3:0];// on basys last from left
DECCOUNT_Disp1 <= MouseDY[7:4];
DECCOUNT_Disp2 <= MouseDX[3:0];
DECCOUNT_Disp3 <= MouseDX[7:4];//On basys first from left
LED_DISP_1 <= MouseStats;
end
Mux Mux4 ( .CONTROL(Bit2Count),
.IN0(DECCOUNT_Disp0),
.IN1(DECCOUNT_Disp1),
.IN2(DECCOUNT_Disp2),
.IN3(DECCOUNT_Disp3),
.OUT(MuxOut)
);
sev_seg_disp Sev7 ( .SEG_SELECT_IN(Bit2Count),
.BIN_IN(MuxOut),
.SEG_SELECT_OUT(SEG_SELCET_1),
.HEX_OUT(Dispout_1)
);
assign SEG_SELECT = SEG_SELCET_1;
assign DispOut = Dispout_1;
assign Led_disp = LED_DISP_1;
endmodule
//16 bit counter module
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:34:45 02/02/2013
// Design Name:
// Module Name: GenericCounter
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module GenericCounter(
input CLK,
output TRIGG_OUT,
output [15:0] COUNT
);
reg [15:0] Counter = 0;
reg Triggerout;
//synchronuos counter logic
always@(posedge CLK) begin
if(Counter == 49999)
Counter <= 0;
else
Counter <= Counter+1;
end
//synchronuous troggerout logic
always@(posedge CLK) begin
if(Counter == 49999)
Triggerout <= 1;
else
Triggerout <= 0;
end
assign COUNT = Counter;
assign TRIGG_OUT = Triggerout;
endmodule
//2 bit counter module
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 01:04:40 02/03/2013
// Design Name:
// Module Name: GenericCounter2
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module GenericCounter2(
input CLK,
output TRIGG_OUT,
output [1:0] COUNT
);
reg [1:0] Counter = 0;
reg Triggerout;
//synchronuos counter logic
always@(posedge CLK) begin
if(Counter == 3)
Counter <= 0;
else
Counter <= Counter+1;
end
//synchronuous troggerout logic
always@(posedge CLK) begin
if(Counter == 3)
Triggerout <= 1;
else
Triggerout <= 0;
end
assign COUNT = Counter;
assign TRIGG_OUT = Triggerout;
endmodule
//Mux module
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:26:26 02/02/2013
// Design Name:
// Module Name: Mux
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Mux(
input [1:0] CONTROL,
input [3:0] IN0,
input [3:0] IN1,
input [3:0] IN2,
input [3:0] IN3,
output reg [3:0] OUT
);
always@(CONTROL or IN0 or IN1 or IN2 or IN3)
begin
case (CONTROL)
2'b00 : OUT <= IN0;
2'b01 : OUT <= IN1;
2'b10 : OUT <= IN2;
2'b11 : OUT <= IN3;
default : OUT <= 4'b0000;
endcase
end
endmodule
//seven seg module
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:47:10 01/31/2013
// Design Name:
// Module Name: sev_seg_disp
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module sev_seg_disp(
input [1:0] SEG_SELECT_IN,
input [3:0] BIN_IN,
output reg [3:0] SEG_SELECT_OUT,
output reg [6:0] HEX_OUT
);
//segment select case statement
always@(SEG_SELECT_IN) begin
case(SEG_SELECT_IN)
2'b00 : SEG_SELECT_OUT <= 4'b1110;
2'b01 : SEG_SELECT_OUT <= 4'b1101;
2'b10 : SEG_SELECT_OUT <= 4'b1011;
2'b11 : SEG_SELECT_OUT <= 4'b0111;
default : SEG_SELECT_OUT <= 4'b1111;
endcase
end
// 4-bit input to 8-bit 7segment display output
always@(BIN_IN) begin
case (BIN_IN)
4'b0000 : HEX_OUT[6:0] <= 7'b0000001;
4'b0001 : HEX_OUT[6:0] <= 7'b1001111;
4'b0010 : HEX_OUT[6:0] <= 7'b0010010;
4'b0011 : HEX_OUT[6:0] <= 7'b0000110;
4'b0100 : HEX_OUT[6:0] <= 7'b1001100;
4'b0101 : HEX_OUT[6:0] <= 7'b0100100;
4'b0110 : HEX_OUT[6:0] <= 7'b0100000;
4'b0111 : HEX_OUT[6:0] <= 7'b0001110;
4'b1000 : HEX_OUT[6:0] <= 7'b0000000;
4'b1001 : HEX_OUT[6:0] <= 7'b0001100;
4'b1010 : HEX_OUT[6:0] <= 7'b0001000;
4'b1011 : HEX_OUT[6:0] <= 7'b0000000;
4'b1100 : HEX_OUT[6:0] <= 7'b0110001;
4'b1101 : HEX_OUT[6:0] <= 7'b0000001;
4'b1110 : HEX_OUT[6:0] <= 7'b0110000;
4'b1111 : HEX_OUT[6:0] <= 7'b0111000;
default : HEX_OUT[6:0] <= 7'b1111111;
endcase
end
endmodule
We use cookies and similar technologies for the following purposes:
Do you accept cookies and these technologies?
We use cookies and similar technologies for the following purposes:
Do you accept cookies and these technologies?