Triple well tie-down rule in IBM 65nm cmos10lpe process

[chickenvlsi]

Hi everyone,
We are using IBM 65nm cmos10lpe process.
Our design used a triple-well RF nfet (nfettw_rf). However, when we checked DRC with Calibre, the tool generated the following result:
"Triple well tie-down rule: [(T3 not over NW) touching gate] must touch RX, which is electrically connected to (RX over NW) through M1"

Could you please explain more about this rule and let me know how to fix the violation of this rule?

Thank you very much

 

[oermens]

You can try asking on MOSIS User Group if you got the PDK throught them:

**broken link removed**