[SOLVED] Triple well layout

[the8thhabit]

Hi I'm currently layout a bootstrap switch and I'm having trouble solving the warning below.
Also, I used the triple well process to apply one body of NMOS to a different voltage (not VSS), and I was wondering if it is correct to layout it like below.

 

[sidun.av]

Hi @the8thhabit ,
1. Could you please annotate your NWELL, PWELL and deepNWELL on the layout? I also cannot see the net4 and the corresponding WELL connected to it which supposed to be the body connection.
2. This WELL doesn't seem to be connected anywhere:

Also, are both WELLs are NWELL type?
3. Did you check both DRC and ERC? Are they both clean?
4. Just a suggestion regarding your schematic - you are connecting the gate of NM0 directly to VDD - this is not a good practice. Connect your gate to VDD through TIEHI cell instead.

Hopefully, that helps.

 

[dick_freebird]

"Stamping" means net assigned (by pin or by rule).

Start with extracted view, grab the net, select objects for net, and work the list until you find the "wrong" object that's pushing a second net name

The extract rules may "stamp" a region if no pin is found.

Extract rules may also key off layout features like "bulk" layer but some will not tell you it wasn't found, and just do a bad extract. Pay some attention to the "non-printing" recognition layers. Read report logs.

 

[the8thhabit]

Hi @the8thhabit ,
1. Could you please annotate your NWELL, PWELL and deepNWELL on the layout? I also cannot see the net4 and the corresponding WELL connected to it which supposed to be the body connection.
2. This WELL doesn't seem to be connected anywhere:
View attachment 198045
Also, are both WELLs are NWELL type?
3. Did you check both DRC and ERC? Are they both clean?
4. Just a suggestion regarding your schematic - you are connecting the gate of NM0 directly to VDD - this is not a good practice. Connect your gate to VDD through TIEHI cell instead.

Hopefully, that helps.

The outer rings are SUB (VSS) and ISO (VDD), respectively, as shown in the photo below.
We have connected the source and body with net4.

I was wondering if I can surround the deep nwell and pwell with iso rings like in the photo.

I pass DRC!

 

[sidun.av]

I would not be able to help you if you wouldn't answer my questions and keep asking yours. Please, answer questions 2 and 3 in full from my previous post.
Also:
1. What nets are rejected for stamping in your LVS?
2. Did you try to trace this net and see if it connected properly?
3. Try to use short isolation in Calibre between VDD and rejected net to localise the issue.

 

[the8thhabit]

I would not be able to help you if you wouldn't answer my questions and keep asking yours. Please, answer questions 2 and 3 in full from my previous post.
Also:
1. What nets are rejected for stamping in your LVS?
2. Did you try to trace this net and see if it connected properly?
3. Try to use short isolation in Calibre between VDD and rejected net to localise the issue.

I have resolved the issue based on your response, thank you for your reply!!

 

[sidun.av]

I have resolved the issue based on your response, thank you for your reply!!

I think it would be useful for the forum to share what was the root cause and how you solved it. Thank you.

 

[the8thhabit]

I think it would be useful for the forum to share what was the root cause and how you solved it. Thank you.

Actually it is problem of not triplewell, just at the other net...
Thanks for your help~!