[SOLVED] Trim circuit (Trimmable Resistor in a BGR design)

Hi All,

I designed the traditional Bandgap Voltage Reference based on the banba architecture. (Please, see figure 1). However, I would like to design a trimmable resistor to ensure that my voltage reference will be accurate. I am using TSMC 0.18 um technology
I will not have access to cutting trimming. Maybe fuse trimming is the option.
I dont know how to design the trimmable resistor. What is the easier way to design a trimmable resistor?

Could somebody help me in this issue?

Thanks a lot.

If you have an "analog" foundry flow you probably have at
least one thin-film resistor. Fusible links are just a minimum
width resistor with oversized endcaps and interconnect
capable of supporting the fusing current short term. The larger
effort is designing the sense & switch circuitry, and protecting
the things you -don't- want to blow up, from the blow-energy.

Poly is one option, sometimes you also find thin film resistors
up in the interconnect stack. These latter may have better-
controlled value and tempco than poly. However a high-sheet-
resistance film is more difficult to get the blow-power into.

Gate zap is another commonly supported trim scheme.

For a commercial product you would want to be using whatever
the foundry has already qualified, because qualifying it on your
own will be a long, expensive and risky proposition.

You need to consider having two trims, one for tempco and
one for voltage afterward, to make up for the skew of the tempco
trim.

At one pad per bit the size will be dominated by pads; a serial
interface may not be much smaller as a programming switch
per bit would then take the place of pads. At 0.18 you may
come out ahead, at 0.5um I have seen pad-per-bit come out
more efficient.

If your chip already happens to have a serial interface and
register resources then I would spend my effort on an internal-
programming-switch design.

In a junction-isolated technology you may find using a substrate
BJT to deliver the current works out best. I work mainly on
SOI these days, so no such luck.

Thanks very much dick_freebird for your information.
This is an academic work, and my plan is to send this circuit to fabrication. As there is no other circuits in the die, I think I have many pins available to use.
Please, could you take a look in the trim scheme that I planned to use in my design? (please, figure 2).
The idea is to connect many resistor in series through NMOS switches, controlled by bits 1 to 4. In this way, I can controll the resistance bidirectionally.

Do you think about it? Does it work properly?
All observations are welcome.

thanks again.

That is "software" trimming and it is widely used in industry. Just make sure that your switch resistance is appropriate!

I assume you have to match some resistors of unequal value. I would try to make the resistors out of multiples of some smaller value then add the trimming to make up the difference. As a simple example, suppose you needed a 10k and 11k resistor to match. You could pick 1k and use 10x and 11x to get the two values and be perfectly matched. So, for trimming you need to work out how much mismatch error you need to adjust for. Assume it is 5%, i.e. 500 ohms. So, you could then use 20x500 and 22x500, but instead of doing that, you would use 21x500 plus 1k of trimming. That way you can adjust the 11k from 10.5k to 11.5k. Then most of the resistors would match and the only bit that doesn't is small.

Maybe you could argue you should just make a 10k & 10.5k and if the resistors were that close, there would be an argument for making 10k and 10k+500 ohms plus the 1k trimming. Then the two 10k would be matched.

Just my thoughts.

Keith.

Thanks Joannes, and mainly Keith for your thoughts.

I got your idea... and I had thought about doing something similar.
Now I need to investigate which resistors are better to trim...

Only one question:

I am using high-resistance poly Resistor (because my resistances are very high, for instance, 500k ohms).
Do you know the value of mismatch that I can expect of between `two matched resistors` - applying proper layout techniques.
1%, 5% ?
I didn't find much information about that in the manual.

Thanks very much,

I must admit I don't know my way around TSMC data very well (and they don't seem to want you to find your way round it!).

For another fab I use the matching is given as %um with high res poly being 5.6 (for a 0.35um process). So the SD=5.6/sqrt(W*L). So, if your resistor is 10x100um the SD will be 0.18% so 3SD will be 0.53%. If you use 50x5um then it would be 1.06% for 3SD. These figures would only apply above a certain width and they usually recommend a >10:1 L/W, but I have made DACs which break those rules very successfully (under the fab's guidance).

Keith.

in fact I checked all PDF files I have. But... that is ok.
The formula you proposed is based on Pelgrom model... I think. Thanks very much for your help

Palmeiras

Yes, I looked through the TSMC 0.18um documents and couldn't find it either. I guess you could reverse engineer the Spice matching models (if you could find those!).

Keith.

Just curious, which resistors are you trimming.
Please make sure you at least trim the Vref if you are not too keen to trim the tempco also. Ideally you want to trim for both.

Hi love_analog`
My plan is to trim R1 and R2 (at the same time); in order to achieve the best temperature performance.
What would you suggest?
Thanks!