trigger to 12 clocks - verilog

[digi001]

What is the best way to generate 12 clocks signals from a master clock, once a trigger goes low?

After the 12 clocks the circuit should stop. How would I do this in Verilog?

 

[er.akhilkumar]

I don't understand your question. Please elaborate your question, do you want 12 different clock sources(please indicate their frequency) generated from one master clock or you want 12 clock cycles on master clock after the trigger goes low????

 

[digi001]

No the question is regarding control signals for sequential logic. Say i come up with a sequential circuit which is pipelined and needs 12 clock cycles to complete. What is the best way to get this circuit 12 clock cycles then stop? Should this be embedded into the sequential circuit module, or should this be a separate circuit that generates 12 clock cycles.

 

[TrickyDicky]

the clock runs forever. Never mess with the clocks.
You need to have an enable signal that is high for 12 clocks (or for proper deisgn just keep pumping in data with a valid signal that makes when the output is valid.)

 

[digi001]

Ok thanks. Yes i see what you mean, I should stick to using more of clock enables and let the data continuously flow through with a latency of 12 clock cycles.