library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use ieee.numeric_std_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity triangulartest1 is
Port (clk, reset : in STD_LOGIC;
dac_out : out STD_LOGIC_VECTOR(7 downto 0));
end triangulartest1;
architecture Behavioral of triangulartest1 is
signal flag : natural;
signal temp : unsigned(7 downto 0) := "00000000";
begin
process(clk)
begin
if temp = "00000000" then flag <=0;
end if;
if temp = "11111111" then flag<=1;
end if;
if (rising_edge(clk)) and (flag = 0) then temp<= temp + "00000101";
dac_out <= std_logic_vector(temp);
elsif (rising_edge(clk)) and (flag = 1) then temp<= temp - "00000101";
dac_out <= std_logic_vector(temp);
end if;
end process;
end Behavioral;
Attached below is the schematic of the dac that I am using, and pins mapped (picture in my previous reply) are connected in order from lsb to msb. Even when I reverse the order, the output is similar, voltage is changed(0-0.5V in stead of 9.5-10V). I will try to simultaneously check on the scope each of the bits and the dac output as I have no clue why this is happening.That’s right, you have to make sure that the LSB of dac_out gets mapped to the FPGA pin that’s connected to the DAC LSB pin, etc. The constraint file is half the story, the schematic (or PCB layout) is the other half.
Why not? What does buffer mean here?Theres no reason to declare dac_out as buffer, it’s an out.
Also no reason to use case statement, a nested if-then-else will suffice.
Why are you gating the clock? Do not AND the clock with another signal.Attached below is the schematic of the dac that I am using, and pins mapped (picture in my previous reply) are connected in order from lsb to msb. Even when I reverse the order, the output is similar, voltage is changed(0-0.5V in stead of 9.5-10V). I will try to simultaneously check on the scope each of the bits and the dac output as I have no clue why this is happening.
--- Updated ---
So far what I found out is that as I read pins starting from LSB to MSB, the output waveforms are getting more and more distorted in comparison to the LSB. It seems as if MSB does not go to 0 at any point for some reason. The board is new so I do not believe that something is faulty with the pins, I assume I do not know something about the board and that therefore this is the consequence. Are there particular pins that I should choose maybe?
Also, note that dac_out(7) has to be connected to B1 of DAC0800, dac_out(6) to B2, dac_out(5) to B3, ..., dac_out(0) to B8.Sorry can you please tell me if I understood "pin mapping" term correctly? I googled about the meaning but so far I did not find any explanation. I thought that bit mapping is dedicating outputs from the code to the on-board pins, LEDs, 7 segment etc. Am I correct or I completely misunderstood? Picture for a reference of how I declared the pins on the board in MIMASV2.ufc .
As for the simulation, I am using XISE for coding and simulation.Why not? What does buffer mean here?
dac_out : buffer std_logic_vector(7 downto 0);
Also, what's wrong with using case statement here?
atancic, what simulator are you using? I probably would ask that you show your simulation here.
--- Updated ---
Why are you gating the clock? Do not AND the clock with another signal.
Also, I believe the timing here isn't as expected either. It would be way shorter than expected if your counting starts off in the wrong direction. Confirm that the period of the waveform is correct. Your initialization or count can make your signal start off in the wrong direction. Let's start from here. Initialize flag to 0. With your step size of 5 Set flag to 0 at temp=5 and set it to 1 at temp=250 (I'd prefer to use NOT flag repeatedly rather than explicitly use 0 and 1). Realize that this will cause temp to increase to 255 (i.e. one clock cycle later) before beginning to decrease. And it will cause it to decrease to 0 (i.e. one clock cycle later) before increasing again.
I repeat: you can declare dac_out as buffer. There's no problem with that. You can use case statement with if statements embedded within it or you can use pure if-else statements. The choice is yours.
--- Updated ---
Also, note that dac_out(7) has to be connected to B1 of DAC0800, dac_out(6) to B2, dac_out(5) to B3, ..., dac_out(0) to B8.
process(clock)
begin
if temp = "00000000" then flag <='0';
elsif temp = "11111111" then flag <='1';
end if;
if rising_edge(clock) then
if flag = '0' then temp <= temp + "0000101";
elsif flag ='1' then temp <= temp - "00000101";
end if;
end if;
dac_out <= temp;
end process;
Actually your first reply worked. I swapped the code lines as you suggested and changed the flag triggering limits to "00000101" and "11111010" (5 and 250) and the output is a nice triangular waveform. I also tried incrementing by 1 instead of 5 but the output is nicer when it is incrementing/decrementing by 5 so I .left it as it is. Thank you both @barry and @Akanimo !If it be the case that you have 10V and -10V as peaks of the triangle waveform from DAC0800 (assuming you have a Vref of 10V), then you should just need to change the value 5 in the 5 and 250 combination to a value 5 above halfway of 256. But then a step size of 5 would not be a good value for a quick design testing, so you'd have to change to the appropriate step size of 1 and a 1 and 254 combination in place of the 5 and 250 combination. The combination would now be changed to 129 and 254 to get the triangle wave to be at about 0V to about 10V peaks.
Anyways, when you have made the corrections, post your corrected code let's be sure you understood what corrections you were asked to make, and also post the DAC0800 scope waveform let's see the result. From there, we may have to look at the DAC0800 circuit.
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