library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use ieee.numeric_std_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity triangulartest1 is
Port (clk, reset : in STD_LOGIC;
dac_out : out STD_LOGIC_VECTOR(7 downto 0));
end triangulartest1;
architecture Behavioral of triangulartest1 is
signal flag : natural;
signal temp : unsigned(7 downto 0) := "00000000";
begin
process(clk)
begin
if temp = "00000000" then flag <=0;
end if;
if temp = "11111111" then flag<=1;
end if;
if (rising_edge(clk)) and (flag = 0) then temp<= temp + "00000101";
dac_out <= std_logic_vector(temp);
elsif (rising_edge(clk)) and (flag = 1) then temp<= temp - "00000101";
dac_out <= std_logic_vector(temp);
end if;
end process;
end Behavioral;
Thank you. I have just realised that the program does not know what to do between "00000000" and "11111111", along with other mistakes that you mentioned. Thank you. I will try to correct them along with implementing suggestions from @dpaulYou just said the simulation looks correct. Doesn't that mean the code is ok? Have you looked at signals into the DAC? Are they changing? Is there a hardware problem?
BUT, I'm not sure why your simulation worked, though. You're missing temp in your sensitivity list. Also, what's the value of flag when temp does not equal "00000000" or "11111111"? You have an undefined state. Why is temp 8 bits? It looks like it only has two states.
Also, your code is bad form. You should not have two rising_edge statements.
So, yeah, it looks like you need to correct your code.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Triangular is
Port ( Clock : in STD_LOGIC;
temp : inout unsigned (7 downto 0) := "00000000";
flag : inout std_logic;
dac_out : out unsigned (7 downto 0));
end Triangular;
architecture Behavioral of Triangular is
begin
process(clock,flag,temp)
begin
if temp = "00000000" then flag <='0';
elsif temp = "11111110" then flag <='1';
end if;
if (rising_edge(clock)) and (flag = '0') then temp <= temp + "0000001";
dac_out <= temp;
elsif flag ='1' then temp <= temp - "00000001";
dac_out <= temp;
end if;
if temp = "00000000" then flag <='0';
elsif temp = "11111110" then flag <='1';
end if;
end process;
end Behavioral;
if rising_edge(clk) then
if flag=0 then
Blah...;
else
Blah blah...;
endif;
[code]
Forgive me but I am not into vhdl for a long time, some things that I do are because that is how it was showed to me and most of my knowledge is based on research. The reason why I used temp as inout is to be able to do addition and subtraction.Your code is still wrong
why is temp inout ? You’re going to have multiple drivers.
you STILL have undefined conditions tor temp
why is flag in your sensitivity list?
your “if rising_edge“ statement is a mess. should be something like:
if rising_edge(clk) then
if flag=0 then
Blah...;
else
Blah blah...;
endif;
Making temp inout has nothing to do with addition and subtraction. You're not using it as an input, it’s an output.
i would verify the DAC output in simulation has the proper range. is your DAC 8 bits?
When I declare it as an output I have an error "Cannot read from 'out' object temp, use 'buffer' or 'inout' ", that is why I set it as inout.Making temp inout has nothing to do with addition and subtraction. You're not using it as an input, it’s an output.
i would verify the DAC output in simulation has the proper range. is your DAC 8 bits?
port(
temp: out unsigned...
signal temp_sig : unsigned...
temp <= temp_sig;
[]
what format does your dac use? Straight binary? Two’s complement?
I will use intermediate signal then. I am using DAC800, straight binary.You either have to compile using VHDL-2008 to be able to read outputs, or else use an intermediate signal which gets assigned to the output. e.g.:
Code:port( temp: out unsigned... signal temp_sig : unsigned... temp <= temp_sig; [code] what format does your dac use? Straight binary? Two’s complement?
If it’s straight binary, and your output doesn't go below 9.5v, then your high-order bits are stuck high. There’s no other answer. maybe you’ve got a pin-mapping error. Have you looked at the data bits into the DAC with a scope?I will use intermediate signal then. I am using DAC800, straight binary.
Ugh, didn’t even notice that.I don't understand why you moved the temp from being a signal to temp as a inout port (same with flag, which just appears to be a flag to let you know if you are incrementing or decrementing). Both temp and flag were both fine as signals, not sure why you change them to ports, considering you already had the dac_out port to send your temp data to the DAC.
dac_out is assigned to P6 pins 1-8. The same is used for both square and triangular wave output, however for the square wave generation the output alternates between 0 and 10 as it should.If it’s straight binary, and your output doesn't go below 9.5v, then your high-order bits are stuck high. There’s no other answer. maybe you’ve got a pin-mapping error. Have you looked at the data bits into the DAC with a scope?
When I had changed them to ports, I started to get the desired output from the board. When they are set as signal, the simulation behaves normally however when I flash it to the board and read the output on the oscilloscope it shows a straight line.I don't understand why you moved the temp from being a signal to temp as a inout port (same with flag, which just appears to be a flag to let you know if you are incrementing or decrementing). Both temp and flag were both fine as signals, not sure why you change them to ports, considering you already had the dac_out port to send your temp data to the DAC.
You could still have the pins mapped incorrectly and see this behavior. For “00000000” or “11111111” it doesn’t matter what the mapping is.dac_out is assigned to P6 pins 1-8. The same is used for both square and triangular wave output, however for the square wave generation the output alternates between 0 and 10 as it should.
--- Updated ---
When I had changed them to ports, I started to get the desired output from the board. When they are set as signal, the simulation behaves normally however when I flash it to the board and read the output on the oscilloscope it shows a straight line.
Sorry can you please tell me if I understood "pin mapping" term correctly? I googled about the meaning but so far I did not find any explanation. I thought that bit mapping is dedicating outputs from the code to the on-board pins, LEDs, 7 segment etc. Am I correct or I completely misunderstood? Picture for a reference of how I declared the pins on the board in MIMASV2.ufc .You could still have the pins mapped incorrectly and see this behavior. For “00000000” or “11111111” it doesn’t matter what the mapping is.
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