Trapezoidal Waveform Generator

[knicklicht]

I need to build a trapezoidal waveform generator that has the signal behavior shown in the image:

In words (format: voltage_level1(<duration>) - rise/fall_time - > voltage_level2) :
2.0V (3.5us) - 3.0us -> 23.0V (4.5us) - 1.5us -> 13.0V (9.0us) - 1.5us -> 2.0V (3.5us) - 3.0us -> 23.0V (4.5us) - 1.5us -> 13.0V (4.0us) - 1.0us -> 9.0V (1us) - 1us -> 13.0V (2.0us) - 1.5us -> 2.0V

However, I am totally new to analog signal processing/generating. I found an article that describes the process of designing a trapezoidal waveform generator (http://www.interfacebus.com/transistor-trapezoid-waveform-generator-circuit.html) but it seems to describe a circuit that produces a signal such as:

I have no idea if the used components can generate the required maximum voltage level. Also I do not know if it is suitable for my 42V power supply. I don't know the exact power requirements but I know that the circuit I want to recreate uses two transistors similar to:
http://www.ben.cz/_d/datasheet/thermaltrak-an.pdf and http://www.onsemi.com/pdf/datasheet/njl3281d-d.pdf.
I have the original board and I am willing to sacrifice it to reverse engineer the cuircuit but I was wondering if it is easier to design it myself. Additionally, I need to be able to trigger the trapezoidal waveform signal with a digital 3.3V signal.

Can anyone please point me to the right direction?

 

[betwixt]

I think my approach to generating a non-repetitive but specified waveform like that would be to use an MCU and DAC. Any amplification or level shifting would be done in hardware but could also be controlled by the MCU if necessary.

Brian.

 

[knicklicht]

Thanks Brian. I also read about DACs. So do I understand you correctly: I would buy a DAC component that has the desired resolution and frequency and would generate a low voltage signal. For example I could choose a 10bit DAC that runs at 0 to 3.3V. What kind of hardware would I need to then shift the 0V to the 2V and what kind of amplifier circuit is suitable to generate the 23V. From what I read in the data sheets of the NJL3281D they are rated at 15 AMP, 260 VOLT, 200 WATT which seems pretty high for my applications but this is what I have at hand.

 

[danadakk]

Given the period in the uS range DMA driven table to DAC probably best solution.

This part can do this, very little code needed, eg. code for table values, and DMA setup -

The onchip Wavedac can generate standard waveforms, like sine, tri, saw...and arbitrary
from either a table you supply to project in Excel that compiler programs into its FLASH
memory or a hand drawn waveform in its wizard. I recommend the table. Chip has enough
resources you can do 4 channels of signal generation.

Note you can change table values to alter waveform if needed.

Right hand window shows chip resources used/left. This example is single chip,
most resources available for other work.


Regards, Dana.

 

[knicklicht]

Thanks Dana, that looks promising. I am really new to analog signal generation. What is the software you are using and what kind of hardware is needed to run the Wavedac?

 

[betwixt]

Don't confuse the power rating of a transistor with what it needs to produce in a circuit. Think of the power rating as being the red line on a speedometer, it only says you risk breakdown if you exceed it but anything less is fine.

True, a DAC will only produce a low voltage and you need to increase it to the level you need. That is a fairly straight forward process in itself. Where it gets a little more complicated is maintaining the voltage while it is being loaded by whatever you are driving. The heavier the load, the harder it has to 'push'. It would help us if you could explain what the voltage is used for because different types of load will require different amplifiers and power capability.

Brian.

 

[danadakk]

Thanks Dana, that looks promising. I am really new to analog signal generation. What is the software you are using and what kind of hardware is needed to run the Wavedac?

Its PSOC Creator, it and compiler free -

https://www.cypress.com/products/psoc-creator-integrated-design-environment-ide

This is a traditional IDE and you code in C and/or ASM. You can also use Verilog in
addition to create custom onchip digital HW.

Board to use (if you dont need tons of I/O) $ 10, upper right hand corner -

https://www.cypress.com/documentation/development-kitsboards/psoc-5lp-development-kits

When you click on that link it shows board info, and says its out of stock. I think
thats because they are trying to push sales thru distributors, but I would bet they
would honor an order.

No additional HW is needed, this is a single chip solution.

Other resources on this chip, see attached catalog of its resources.

Lots of other projects in IDE and here -

PSoC-4-BLE/100_Projects_in_100_Days at master · Infineon/PSoC-4-BLE

PSoC 4 BLE is an easy-to-use, ARM® Cortex™-M0 based, single-chip solution which integrates programmable analog front ends, programmable digital peripherals, CapSense® technology for touch-sensing, ...

github.com

GitHub - Infineon/PSoC-6-MCU-BLE-Connectivity-Designs: The examples in this repository demonstrates PSoC 6 MCU with BLE Connectivity based Bluetooth Low Energy (BLE) connectivity feature.

The examples in this repository demonstrates PSoC 6 MCU with BLE Connectivity based Bluetooth Low Energy (BLE) connectivity feature. - GitHub - Infineon/PSoC-6-MCU-BLE-Connectivity-Designs: The ex...

github.com

https://www.cypress.com/documentation/code-examples/psoc-6-mcu-code-examples-psoc-creator

Here is example of creating burst waveforms, same chip.

Test Bed DDS and WaveDAC burst tool

Occasionally I need to generate custom wave forms and burst a known number of cycles into a DUT. This is a single chip solution, board I typically I use is $ 10. You just drag and drop components onto schematic, wire internally with a wire wizard tool and out to pins, right click and config...

www.edaboard.com

Regards, Dana.

 

[dick_freebird]

If you need just the waveform and not the experience of having built the source, have a look at the "Feeltech" series of signal generators selling cheap on eBay. I picked up several and they have, besides the usual "canned" waveforms, a reasonably deep AWG which you can program over the USB port.

 

[knicklicht]

I actually have an FPGA at my disposal (Zedboard). It might also make sense to just buy a PMOD DAC and attach it to the board as an alternative to the PSoC5 approach. I'll have to check what would be the cheaper solution.

I found a cheap used FreeSoc2 (https://www.sparkfun.com/products/13714) for 25€ (I am from Europe). Would this work with your approach Dana? Ordering directly from Cypress might be to expensive for me, due to shipping.

Either solution would take care of the signal generation but I am still unsure of how to amplify the signal to the desired voltage range at the needed power level. I am trying to drive an inkjet print head with the signal. For those of you who don't know, some print heads contain an array of piezo elements that drive one print nozzle each. I need to drive a couple of thousand nozzles. It's actually pretty amazing what kind of miniaturization is possible nowadays. Let's assume 10mW per nozzle at 5000 nozzles that would mean 50W.

 

[danadakk]

FreeSOC2 would work fine. I thought Cypress, now Infineon, had offset
shipping costs for EU, if needed try their online store and see what costs
look like to ship.

The amp, what is C load and Vpk-pk needed ?

The FPGA and a DAC would do as well. Development time might be a little
longer....


Regards, Dana.

 

[knicklicht]

How can I find out? I know that the circuit I try to recreate uses something in the order of:
http://www.ben.cz/_d/datasheet/thermaltrak-an.pdf and http://www.onsemi.com/pdf/datasheet/njl3281d-d.pdf mounted to a thick piece of aluminium. here is a picture:

 

[danadakk]

You would need the piezo nozzle datasheet to get this info.

Regards, Dana.

 

[BradtheRad]

A 4017 IC (decade counter) can create an arbitrary waveform by adjusting resistor values at the outputs. The resulting signal can bias a transistor in order to drive a load.

The clock is 1 MHz.
LED's or diodes isolate outputs from each other.
Add a switch of some sort to obtain the brief dip shown in your image where Q7 or Q8 occurs.

 

[danadakk]

This might help on amplifier -

https://www.analog.com/media/en/technical-documentation/application-notes/an18f.pdf

Regards, Dana.

 

[psoc77]

You can find example of the PSoC5 trapezoidal signal generator here:
Trapezoid generator with adjustable rise/fall/amplitude/frequency up to 1MHz?

YouTube demo:

 

[psoc77]

The trapezoidal generator is written in Verilog, and consists of two DDS generators: one to control output frequency (duration), and another to control ramp frequency (risetime). The output bus is driving 4-bit R2R DAC, which output amplitude is controlled by the driving voltage V_analog. Code is attached. If you have a ZED board, it is not so hard to duplicate it.

On the other hand, I recollect that HP (Agilent at that time) was selling a driver chip for its jet printer PZT heads. I would google it first.

 

[knicklicht]

Thanks for all the suggestions. I will try to build my own DAC + amplification later on. After a summer break, I am still trying to figure out the original circuit design. I have followed the traces and created this circuit diagram:

However, I do not know what the SOT packaged transistors are and the TO package connections make little sense to me. Does anyone know what they contain specifically or how I can find out? Does the circuit diagram make sense? I tried measuring the TO package pins with a multi meter diode tester. I got the following result:

positive -> negative​	1​	2​	3​	4​	5​
1​	NA​	0.57​	0.57​	0L​	1.13​
2​	0L​	NA​	1.77​	0L​	1.95​
3​	0L​	0L​	NA​	1.95​	0.57​
4​	0L​	0L​	0L​	NA​	0.57​
5​	0L​	0L​	0L​	0L​	NA​

The 0.57V voltages should be the foreward bias, but what about the voltages above 1V. I think there also is a temperature dependence as the voltages above 1V increase when I hold the package.

 

[FvM]

I guess, the TO package contains a NPN/PNP transistor pair with common emitter pin.

It makes no sense to design a driver without knowing the piezo actor parameters.

 

[D.A.(Tony)Stewart]

A 4017 IC (decade counter) can create an arbitrary waveform by adjusting resistor values at the outputs. The resulting signal can bias a transistor in order to drive a load.

The clock is 1 MHz.
LED's or diodes isolate outputs from each other.
Add a switch of some sort to obtain the brief dip shown in your image where Q7 or Q8 occurs.

View attachment 170796

Nice try. Perhaps a mixed integrator with TG's and OA with push-pull followers inside the loop.

--- Updated Sep 10, 2021 ---

Creating a trapezoid with defined time intervals, levels and slopes with tolerances well defined, is not hard to MUX with integrators and level switchers, but the dV/dt must know the load capacitance Ceq, ESR and ESL of layout. do you have any /all of these?

the shape might not be importance in the end if envelope rise time and decay time are factors. Rather Q and BW

--- Updated Sep 10, 2021 ---

Creating a trapezoid with defined time intervals, levels and slopes with tolerances well defined, is not hard to MUX with integrators and level switchers, but the dV/dt must know the load capacitance Ceq, ESR and ESL of layout, effective BW.. purpose... does OP have any /all of these?

 

[D.A.(Tony)Stewart]

Again, you must define the load impedance Z(f) or equivalent circuit. These complementary BJT transistors enhance efficiency and lower output impedance by 3 methods. (NFB, Temp balancing by eliminating are, and parallel BJT emitter followers (complementary AB a biased)

This is useful in their linear audio design to improve THD by 30dB . All of these methods rely on impedance ratios of source to load including your trapezoid ramp of Ic=CdV/dt which is why C,R,L parameters of load are so important. yet we know nothing of your application except the shape of signal and BW is inverse to the slope, f-3dB = 0.35/Tr with dV/dt = 10V/1.5us
The built in diodes could also be made with discrete parts, readily available, but these look good for 30 mOhms in a Vce(sat) condition nominal plot of Vce(sat)=300mV @ 10A yet the tables indicate 3V max !!!

however you can get much lower RdsOn in FET's as voltage followers but with more complex biasing if complementary. But does it need complementary? Yes because you have a some TBD reactive load.
We need a hint.

The trapezoid waveform is relatively easy for me to synthesize with common discrete parts + simple IC's if you had tolerances. I have done similar on to synthesize Infineon smart wheel speed encoders (WSS) with current sourced sync and Biphase data.