Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Transition Delay Fault Methodology

Status
Not open for further replies.

Haji-

Newbie level 4
Newbie level 4
Joined
Feb 16, 2010
Messages
7
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Location
Silicon Valley, CA
Activity points
1,323
When using Transition Delay Fault model, there are 2 schemes:
- Launch on Capture
- Launch on Shift

When do we have to make this decision?
What do we need to consider making a selection?
Can we implement both on a given netlist?
What is the impact on test coverage by either methodology?
 
Last edited:

Hi Haji,
We can inplement both LOC and LOS on a given netlist. It depends on the commands which we are using in ATPG.

LOS will generate the basic patterns and will have high coverage.But due to transition on scan enable between launch and capture it will be difficult to meet the timing and this is less preferred.
 
  • Like
Reactions: Haji-

    Haji-

    Points: 2
    Helpful Answer Positive Rating
Hi Honey13,

Can you Plz elaborate on the STA problem we face when SE toggles, actually Iam not able to figure out the need for a new STA mode which has been created for timing closure of a legacy chip on I have started working....?


Or in other words , what special timing check is performed in STA for TFT mode which is not covered in i) Functional Mode and ii) Scan Shift Mode
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top