Alex Liao
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Hi,
A current source load has two matched nmos (in figure 1) and its working OP are shown after pre-layout simulation. The OP are similar between M3D(MM0) and M4D(MM1).
But in post-layout simulation, the OP are not matched using only 2 fingers for each nmos. Please refer figure 2 for M3D and figure 3 for M4D.
First, the Vgs of MM0 is different from MM0@2 so does the id. The OP state of each finger of M3D is not the same as the other one. Second, even there is small differences of OP for each finger of M4D (MM1 and MM1@2), the M3D(MM0) is totally different from M4D(MM1) in respect to OP print.
Is there anybody who encounters those similar mismatches between schematic-level and post-layout simulation in tsmc 65nm?
Thanks,
Alex Liao
A current source load has two matched nmos (in figure 1) and its working OP are shown after pre-layout simulation. The OP are similar between M3D(MM0) and M4D(MM1).
But in post-layout simulation, the OP are not matched using only 2 fingers for each nmos. Please refer figure 2 for M3D and figure 3 for M4D.
First, the Vgs of MM0 is different from MM0@2 so does the id. The OP state of each finger of M3D is not the same as the other one. Second, even there is small differences of OP for each finger of M4D (MM1 and MM1@2), the M3D(MM0) is totally different from M4D(MM1) in respect to OP print.
Is there anybody who encounters those similar mismatches between schematic-level and post-layout simulation in tsmc 65nm?
Thanks,
Alex Liao