To check the cell performance (verification) you have to simulate it, e.g. with HSpice. You need a netlist and model files and .extract statements for the relevant performances.
To size the transistors, there are basically two approaches:
1) symbolically approximative: you start with simplified transistor model equations and develop equations that approximate the relevant circuit performance metrics as functions of the device geometries, then solve for the geometries. Effort, difficulty and accuracy depend on the circuit and model. It's often easy for AC and DC, but not for TRAN specs. For large memories you also have to take local Vt variation into account.
2) numerically: you run a circuit optimization program that runs HSpice in a loop and tunes the circuit for you, to fulfill the specs and reduce process sensitivity.
The first method works well for small low frequency analog designs and is taught in analog design classes and student text books extensively, to improve student's circuit understanding. The second method is the one that works for advanced node RF designs, post-layout tuning, high-speed I/O, full-custom digital, standard cells, large complex analog blocks. It is usually not taught at university.
My company sells circuit optimization tools, see
www.muneda.com to find more information about this topic.