Transistor Level Layout Tool

[shm]

Hello
Is there any tool which can draw my transistor level layout, by a verilog netlist?
I have used tools like Microwind but this tool isn't complete and there is no way to limit size of layout and it isn't very clever in drawing automatic layout so it will providing a big layout which is not acceptable in area size!!

 

[jimjim2k]

Hi

If you want to have IC layout from transistor schematic it is more practical than direct from Verilog to Transistor layout.
Tools starting from verilog (RTL, Behavioral, ...) result in gate level logic using sea-of-gates and standard cells.

If you want study on schematic to layout:

schematic-driven layout in cadence
h**p://www.ee.ucla.edu/~dejan/ee115c/ee115c_tut_4.htm
*-> t

or
micromagic sue-max combination
h**p://bwrc.eecs.berkeley.edu/classes/ICDesign/micromagic/tutorials/sue/old/Sue_tutorial.html#pgfId-1019946


jimjim2k

 

[shm]

Thanks a lot.