transistor level d flip flop

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urimi

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Hi Friends,

Can any one tell me the transistor level circuit design for this truth table, let me know how to implement

Regards,
Urimi
 

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Thank you FvM.........

I want to design a d flip flop with positive egde triggered, low asyncronous reset and set and only one output q with using nand gate. could you please give the suggesions for implementation.
 

As discussed in the linked threads, edge trigger requires master-slave topology. Gate level implementations are given in the links, you should be able to modify according to your needs.

Needless to say that there are many text books out there covering the same topic.
 

I don't have digital IC design books (not my business). I see a detailed discussion of flip-flop circuits e.g. in Enoch O. Hwang, Digital Logic and Microprocessor Design With VHDL. But it doesn't cover the transistor level topic.
 

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