Transistor and current ratios

[aryajur]

If we have 2 MOS with exactly the same VDS and VGS, the same Lengths, but Widths in the ratio say 25:1. Why shouldn't the currents be in the ratio 25:1? I am asking this because simulations don't show the current ratio to be 25:1.

 

[BigBoss]

Channel length is very short regarding to width. It's possible to be channel length modulation effect. Or Vt can be related on W/L ratio.
For MOS transistors, the theoritical values can vary with other physical parameters.

 

[aryajur]

Channel length is very short regarding to width. It's possible to be channel length modulation effect.

The VDS is the same for both. I have done simulations in Subthreshold and Saturation.

 

[Hughes]

The effective channel width is different to the drawn channel width. If you want a 25:1 ratio, you should 25 unit cells / one unit cell. In the schematic, you can set the "m" parameter to 25.

 

[aryajur]

That is true but then the ratio should atleast be close to 25, rather than shooting for 40 or so. Also howmuch of these effects does the BSIM model capture?

 

[hebu]

Do you check the Vth?, the threshold will be effected by aspect ratio.

 

[wangyufn]

I think the most probable reason is channel length modulation. Cascade current mirror can improve the current match.

 

[hebu]

aryajur just told us he controlled the two transistors with the same
vds. So channel length modulation should not be the problem.

 

[borislee]

first, check whether the Vgb are the same and other things you have ignored
second, BSIM3 is offen used for deep sub-micro MOS. The DW/DL (difference between effective width/length and drawing width/length) is possibly comparable to the shortest length. You can use two MOS with larger width (still in the ratio of 25:1) and check whether the current ratio is closer to 25:1.

 

[Hughes]

Firstly, if you use very small width (close to minimum allowable size), DW will make greate difference.
Secondly, if you use binning model, the model itself may be not contineous. The transistor with 25x width and that with 1x width may fall into two different bins.

 

[alchen77]

maybe model use a LUT, the MOS size you used maybe located in different block

 

[aryajur]

The model only has 1 block. Its a 0.5um process and the widths were 4um and 25x4um, Its true that the ratio does get better on increasing the widths but is is still like 30 or greater.

 

[Karthikeya]

check to make sure whether both the transistors are in saturation...can u post the schematic here?
i hv tried in 0.25u it shows minor variation abt 2uA for 400u-450uA current. check the circuit ...probly the load may be very low

regards