transferring data safely

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sun_ray

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Two designs are clocked with 100 MHz clocks with different clocks being generated from different individual oscillators. Can you suggest a technique to safely transfer the data from one design to the next design?
 



These links suggests practices to transfer data. But there is a different and more simple solution to my problem that was sataed in the question. I am looking here for that simple and different solution.

Can you think of a simpler solution for my problem?

Regardrs
 

sun_ray said:
...there is a different and more simple solution to my problem that was sataed in the question. I am looking here for that simple and different solution.
Click to expand...

Well so you know about that more simple solution and still asking? Is it an examination?
If you want to transfer just one signal, use the first link. If you want to transfer a bus, use FIFO link.
 
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    FvM

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Can you think of a simpler solution for my problem?
Click to expand...
Although I generally agree with jirika that the solution is most likely contained in the previous threads, it's not clear what the present problem exactly is, particularly we don't know the kind of data.
 

jirika said:
Well so you know about that more simple solution and still asking? Is it an examination?
If you want to transfer just one signal, use the first link. If you want to transfer a bus, use FIFO link.
Click to expand...

It is not in that way. I am not taking any examination. I do not know the answer so, I am asking.

Your answer of transferring one signal and using FIFO is the traditional answer. Can you please think and get a solution, if you want?

- - - Updated - - -

FvM said:
Although I generally agree with jirika that the solution is most likely contained in the previous threads, it's not clear what the present problem exactly is, particularly we don't know the kind of data.
Click to expand...

Problem is clearly stated. There should not be any complexity in that. Jirika's answer id a traditional one. You may get the solution in a different way if you think of ways other than the traditional ways.
 

FvM said:
Not at all. The simple question asked by jirika (single signal or bus) hasn't been answer.
Click to expand...

It is bus.

I stated data in my question. This data need to be understood in a general purpose and in a general purpose it is bus.
 

Yes you are right. There is more simpler solution. Just connect them together and start praying.
 

two designs such block1 and block2 getting clocks clk1 and clk2 with same frequency 100MHz but from different source, then both clk1 and clk2 are asynchronous.
The data crossing from clk1 to clk2 must be synchronized with valid synchronization scheme.

1) If each bit of bus are ir-relavent(independent) of each other then you can synchronize each bit separately by using two back to back flipflops.
2) You can use handshake based synchronizer if data is not changing rapidly. In this scheme, you will find when data_bus has changed. You synchronize this information to destiination side. When destination acknoledges then you will allow data_bus to change in source domain.
3) 2 clock FIFO

sun_ray: Still you have not described your problem correctly.
 
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    FvM

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Hi,
In reality, as 2 source of clock are used you will not a small phase drift between the two clock.
If this shift is too slow, you can consider your system as mesochornous and use mesochronous synchronizer for transferring your data from one block to another
 

AdvaRes said:
Hi,
you will not a small phase drift .
Click to expand...

Will the word be not or something elas? Can you please provide the correction so that we understand.

How does a memochromous synchronizer look like?
 


Sorry,
I meant you will have a small phase drift between the two clocks. This drift may be so slow such that, with simple assumptions we can consider the system as mesochronous. For more information about that, search with google. There are plenty of papers in the www.
 

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