I am seeing transition violation on output pin of the cell even though input pin transition and output load is fine.
Input pin transition is good output pin load is small. I am seeing transition violation on output pin of the cell. I am not getting the reason for this issue
For ever signal having transition period we will calculate cell delay based on input transition and output load.
we will put some transition limit for every pin if transition of signal is greater than our limit then we report the signal as a violated path.
I suppose the max_tran limit is coming from the values specified in the .lib. So even though the output load looks small, you need to check what is the max value specified in the lib and perhaps your load exceeds this one, hence the violation.