Tran switching to single inner/outer iteration (LDD) mode at time=X

[rockykumar]

I am trying to do a pre-sim of Sigma Delta ADC using HSPICE in 0.18um technology.
What I encountered is the simulation keeps stopping at a particular time for the same setup.
I know I should check the results of before the event of error, which I will do for sure. But what I am curious is, if it is a normal problem encountered with multi threading feature in HSPICE simulation.

The error I encountered is also shown in the attached picture:

8.2% time = 13.448015 ms ( etc = 1:04:22, ett = 1:10:09 )
( wall = 5:46 cpu = 1:26:15 s=14.9401 )
Tran switching to single inner/outer iteration (LDD) mode at time=0.013505 1.2e-12 , wait rebuilding

Error: Convergence Failure ... exiting at time point 0.0135051

>error ***** hspice job aborted

 

[BradtheRad]

Convergence failure pops up for unexpected reasons. Sometimes it's because a device tries to output a state when that state cannot be determined because its inputs are not yet definite. This tends to occur early in the simulation.
Such devices in a delta-sigma ADC could be:
* flip-flop
* op amp
* logic gate
* counter
etc.

Try defaulting each input high or low with a high-ohm pullup/down resistor.

 

[rockykumar]

Thanks, I checked with the OPA to find the reason. I found its due to OPA's gain bandwidth which I have to increase to solve this issue.