Tran keyword in Verilog

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jdshah

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Hello,

I do not completely understand use of tran keyword in verilog.

Example :
tran c (a,b);

Explanation says
The tran switch acts as a buffer between the two signals a and b. Either a
or b can be the driver signal.

My question is if a and b both are connected to some different signal, who will decide which will be the driver signal. Who will win?
 

It can be used to connect a signal with one name to a signal with another name without regard to direction. In most cases, the tran construct can be replaced with the alias construct in SystemVerilog. In either case, all the drivers on all the connected signals behave as if all the drivers had been connected to the same signal.
 


Hi Dave_59

Thanks for reply.

I still do not fully understand.

You mean to say that in tran c (a,b) . a and b behave like it is connected to same driver.

But what is a and b is connected to different signal in reality.

Please explain for this example.
 

I mean to say that a and b behave as if they are connected to the same set of drivers.

Code: 
module top;
   wire [2:0] busA,busB;
   reg [2:0] A,B,C,D;
   reg [3:0] sel;

   bufif1 i0[2:0] (busA,A,sel[0]);
   bufif1 i1[2:0] (busA,B,sel[1]);
   bufif1 i2[2:0] (busB,C,sel[2]);
   bufif1 i3[2:0] (busB,D,sel[3]);

   tran t[2:0] (busA,busB); 
// same as
   alias busA = busB;

endmodule // top
 


Thank you for reply sir

I understood that alias can work like an assign statement for bi directional port.

But what will happen if busA and busB is connected to different drivers. They will have different value then, whose value will be assigned to them.
 

The drivers will be resolved the same way multiple drivers are resolved when connected to the same signal. The point of the tran and alias constructs is you now have one signal with multiple names.
 

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