have you ever faced any problem or difficulty when you tried to link
and integrate some individual verilog modules together?
I was using H*D*L*designer for this purpose but I felt that it's not
user friend enough!
I'm looking for some powerful tool or script (for example in perl)
to do the job very nice and easy!
If you have to integrate and link a lot of
verilog module that are written by other
guys with lots of interfaces you'll see that
its not that easy! I know that I can do it
in a text editor manualy, but I'm seeking
a better way to do it. for example, if all
of team members obey certain rules
for naming their modules interfaces,
then there should be an automated
way to link all the design very soon,
easy and reliable.