[SOLVED] Too fast for 24Mhz logic analyzer?

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Flash chip too fast for 24Mhz logic analyzer?

Hello, just a quick noob question if I'm making the correct conclusion about this problem.

I'm trying to probe 75MHz SPI Flash using 24MHz logic analyzer(Saleae knockoff).
This is probably a dumb question, but I'm getting somewhat erratic CLK signal(attached image) with every sampling frequency(1-24MHz). Is this because the logic analyzer can't keep up?
Are CLK signals always just pure square wave? Why is there a distinct pauses in that signal I got?

Can I read these fast flash chips at all with this, is there any workaround? What kind of device would I need for this?
The 24MHz limit seems to make this analyzer pretty useless in most cases...

This is the flash chip:
WINBOND 25016BVS1G
**broken link removed**
"SPI Clock frequencies up to 75MHz."
 

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The interesting parameter is the actual SPI bus clock frequency, not the maximum rate of 75 MHz. You should also probe the CS line.
 
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FvM said:
The interesting parameter is the actual SPI bus clock frequency, not the maximum rate of 75 MHz. You should also probe the CS line.
Click to expand...
Good point!
I realized that my UT61E multimeter has frequency option, so I probed CLK line and got solid 9.3MHz. The RTL8196C(the device's main IC) datasheet says:
Targeted SPI Flash Frequency: Up to 78MHz (when the SDRAM clock is 156MHz)
SPI Clock = (SDRAM Clock) / (SPI_CLK_DIV)
000: DIV = 2
...
111: DIV = 16
Click to expand...

So I reckon that 156/16=9.75MHz might indeed be the actual CLK frequency.

I attached CS probe, and suddenly I got some (seemingly) valid data!

Does this waveform look like legit data? The CLK line is still waving around between exactly 8MHz/12MHz for some reason. I'm not sure is that normal(which is my main question in this topic).
Could it be, that the 9.75MHz isn't divisible by my logic analyzer 24MHz? Should it matter?
 

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  • clk.png
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Last edited:

The essential point is if you are possibly missing clock cycles. With a clock frequency below 12 MHz, this won't be the case (assuming 50 % clock duty cycle). As a quick test, all SPI transactions should have an integer multiple of 8 clock cycles. Looks like it is.
 
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