Toggling the MCLR pin between VPP and GND during ICSP

[UroBoros]

PIC ICSP doubt

Hai


I have a clarification to get .

Will the MCLR pin have to be toggled between VPP and GND during ICSP programming(by the ICSP hardware). or it has to be toggled only between Vpp and Vdd?.

My target board has pull up on MCLR (as usual) and ICSP programmer supplies Vpp during programming. But how the circuit will reset the pic during programming or is it not needed (reset) during ICSP programming ?
please
Picstudent

 

[silvio]

Re: PIC ICSP doubt

Inside this document you'll find exactly what the doc's name said:

AN910 - PICmicro® Device Programming: What You Always Wanted to Know (But Didn’t Know Who to Ask)
https://ww1.microchip.com/downloads/en/AppNotes/00910a.pdf

Regards,
silvio

 

[bimbla]

Re: PIC ICSP doubt

If you are referring to the circuit I posted elsewhere, don't worry, it will reset the PIC and do all the reqd. job.

bimbla.

 

[UroBoros]

Re: PIC ICSP doubt

hai

thank you very much for suggessions.
Actually I have used the circuit using 74HCT125E buffer.

The logic levels on all the pins are satisfactory on JDM hardware testing.

But for PIC16F877 it is programming ok. But not verifying correctly.I have checked with another programmer.

But I have to use it with 16F73 and in that case it is not at all programming.

I was asking about MCLR because in my target MCLR pin never goes to GND.(Either we have the Vcc through pull up or we have VPP from programmer).In one literature I have read that during ICSP, MCLR have to be toggled between Vpp and GND.
As it is not working with 16F73 any guidelines

Picstudent

 

[M!k]

Re: PIC ICSP doubt

according to the Microchip PIC16F7x FLASH Memory Programming Specification
https://ww1.microchip.com/downloads/en/DeviceDoc/30324b.pdf
the voltage at MCLR has to raise from VIL (= Gnd) to VPP:

The Program/Verify mode is entered by holding pins
RB6 and RB7 low, while raising MCLR pin from VIL to
VPP. Once in this mode, the user program memory and
the configuration memory can be accessed and programmed
in serial fashion. (RB6 and RB7 are Schmitt
Trigger Inputs in this mode.)
The sequence that enters the device into the Programming/
Verify mode, places all other logic into the RESET
state. All I/O pins are in the RESET state (high impedance
inputs).
A device RESET will clear the PC and point to address
0x0000. The ‘Increment Address’ command will increment
the PC. The ‘Load Configuration’ command will
set the PC to 0x2000. The available commands are
shown in Table 2-2.

Perhaps you can try if it works when the crystal is short-circuited to prevent an oscillation which increases the PC.


Mik