to make instruction fast,which instruction type would you pick? Why?

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Revendra Kumar Lanje

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Assume the current-generation processor has the following instruction latencies:

loads: 4 cycles
stores: 4 cycles
adds: 2 cycles
multiplies: 16 cycles
divides: 50 cycles

If for the next-generation design you could pick one type of instruction to make twice as fast (half the latency), which instruction type would you pick? Why?
 

The answer to this question is not so simple, particuarly due to each type of application certain instructions are more or less frequently used, and also the latency of some of them is not fixed, but depends on its arguments. For example if your goal is to use this in a DSP core architecture, will have to focus much efforts in the multiplication and division instructions.
 

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