to create test bench in vhdl - how ?

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rashmi.imhsar

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How do I create a test bench ? Simulating in model sim and seeing the waveform is what is called a s test bench ??

How different should a test becnh code be from my original vhdl code ?
 

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hey,

Both the links are not opening.

And yes I am from India. So are you?

- - - Updated - - -

Actually my code works in hardware. i.e I can see the output by the blinking Leds. But when I tried to run the code in Modelsim,the output values become undefined.

What could be the problem?
 

Undefined "U" or more likely "X" propagation. You probably have some uninitialized signal in your UUT that is propagating an X to the outputs. Post the code and we can help you find the problem signal or just use Modelsim to trace the X back through the design.
 

rashmi.imhsar said:
Both the links are not opening.
Click to expand...
Well, one link was working and the other indeed was not working (the "ml" at the end went for a walk or something). Fixed the one link that didn't work, and left the already working one as is. So you can view those now.

Actually my code works in hardware. i.e I can see the output by the blinking Leds. But when I tried to run the code in Modelsim,the output values become undefined.
Click to expand...

Sounds like a simulation mismatch. That is usually because in your testbench you have not defined the initial state of registers properly. In real hardware it will work, because there the initial state of registers will typically be set to zero after configuration. For it to work the same in simulation you have to do this initializaton.
 

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