TL494 DCDC converter wide range input issues

you really need to test the start / bootstrap ckt as prev described, under hard start - hopefully it is 190V proof (?)

next likely is the ( unseen by you ) surge current at start due to no soft start or pwm limit - at hard start - heating the diode, and then the fet and then - poof - this gets worse for higher Vin step

What is also unseen by you is any ring up on the Vin when suddenly applied - this could be a slightly wonky psu that goes up a bit in response to the sudden load, or an LC ring up if supplied by a real battery ( we can't see the full real ckt )

matters are probably exacerbated by the unknown quality of the gate drive - 200mA is too little drive - and we don't know if it holds the gate off properly either, as the source falls rapidly

the gate drive IC may be misbehaving for > 140 Vin step applied, due to dV/dt

a lot of little and not so little things can come together to make a ckt go bang for > 140VDC applied suddenly

EP

" C12 relies on empty output capacitors and can only be charged with (negative) current through L1. "

the current is not negative.

also - what does this mean ?
" The power supply for sure has a current limit on power up. "

" While you're at it, the VFB dividers are drawing a few watts, so scale up x10R. "

is this true ? 12^2 / 10k = 144/ 10,000 = 14.4 mW (?)

Easy peasy said:

" C12 relies on empty output capacitors and can only be charged with (negative) current through L1. "

the current is not negative.

Click to expand...

Thanks for pointing it out. Yes, you are right. Don´t know how I came to this conclusion.

Easy peasy said:

also - what does this mean ?
" The power supply for sure has a current limit on power up. "

Click to expand...

The datasheet for the BSS126 says: 7mA min current .. up to absolute maximum of 85mA pulse current.
This means it takes time to charge the capacitor. and 85mA @ lets say 150V gives a huge 12.75W.
For 150V the SOA shows a max of 65mA .. but only for 10us.

Again: "at power up", this means the output is considered much below 12V, so there is no current flow through D6.

Klaus

Klaus may well be correct about the inability of the boot strap psu to deliver up to 12V quickly enough - due to the resistance of the very small depletion fet - and its undoubted extra heating as it has to block more and more volts, causing R-ds-on to go even higher than 700 ohms - thus the main fet will not get sufficient drive voltage on its gate and will heat during start up - this can easily be tested with a scope on Vout and the output of the boot-strap start ckt at power up.

Easy peasy said:

Klaus may well be correct about the inability of the boot strap psu to deliver up to 12V quickly enough

Click to expand...

That was my original thought about the source of issue.

Thus I have compiled a list of new changes and new schematic

D2 -> ST5L300, Schottky, 5A, 300V
Q2 -> CPC3980, Depletion nfet, Bigger package (SOT223), a lot smaller RDSon (40ohm), 5x the current, better cooling than current BSS126
Q5 -> IRFS4227, Bigger package, better ciss/crss ratio (less prone to self turn on), 10x lower RDSon, better power dissipation
U3 -> IR2181, half bridge used only with high side, 10x the power, 1.9A
C12 -> 100nF, halved the boostrap cap capacity
R20, R21 -> scaled VFB caps 10x
NEW: C20, R22, R23 -> Soft start circuit calculated for 48%, and ~100 cycles
R17 -> 47 ohm, increased current limit of startup circuit twice (not sure about this yet, will try to scope current one)
R18 -> 9.1k, increased slightly voltage for startup circuit
Q1 -> MMBTA92, just in case, capable of withstanding higher voltage






Original V1.5 layout, yes i am aware it can be done better but i have limited space and have to work around gigantic caps on the board on the other side:

Is there an LC filter supplying this board ? i.e. between the batt and a the board?

p.s. the volt sense resistors were fine as they were, < 15mW ( see above )

Easy peasy said:

Is there an LC filter supplying this board ? i.e. between the batt and a the board?

Click to expand...

No, its directly connected to battery.

How about the changes i made? Looking good? Any suggestions?

time will tell

Finding appropriate Schottky diode has proven to not be trivial. All high voltage schottkys have relatively high Vf which is far from ideal but I came up with 3 candidates:
CI04S65E3, IV1D06006P3, STPSC4H065B-TR

Schematic remained pretty much the same with exception of D2 which above candidates i have in cart.

when it comes to layout, here is what i cooked up, suggestions appreciated:



Hot loop red arrow

3D view:

Hi,

We need to get a step forward. To locate the problem.

Try this:
Use a seperate power supply of about 12V and power up your STARTUP node.
Now the ICs should be properly powered up .. and running, even the bootstrap circuit.

Now do different tests with powering up +BATT node.
The resupts show you if the problem is caused by IC startup or by the power stage around Q5.

***
I still think thea STARTUP is not a good description for this node. It is not used only during strtup but all the time. It simply is a power supply.

***
and yes, I agree that the PCB layout is ot optimal. I miss a clear solid GND plane with all components on the opposite side. You say lack of space, but there still is a lot of space on the TOP side ... but you use it to "sew" the GND fragments on TOP and BOTTOM side together. ... Which will never be as good as a solid GND plane on a SINGLE side.

Next important is a clean, straight (or low area) power path: Input --> capacitors --> Q5 --> D2 --> L1 --> capacitors --> output. (When Q5 is ON)
but also: GND --> D2 --> L1 --> capacitors --> GND (when Q5 is OFF)

Next is Q5_Gate path ....

Klaus

KlausST said:

We need to get a step forward. To locate the problem.

Click to expand...

Yes I would love to do so however there is one big problem.

I do not have power supply capable of outputting 160V+ with current limit which means this test would be one-time only. And this is last mosfet i have so i would prefer to do it non destructive way.

What I can do is to supply startup circuit with 12V and power whole thing with bench PSU (up to 60V) which does have current limit (but then again it doesn't trigger destructive effect)

KlausST said:

lot of space on the TOP side

Click to expand...

There is a bit of space but not a lot, capacitors are not movable, top and bottom is occupied by massive copper busbars.


I am already bending rules a bit by making cutout in bottom busbar, may need to stack it.
Those paths are suppose to carry over up to 150A

Zac1 said:

There is a bit of space but not a lot, capacitors are not movable, top and bottom is occupied by massive copper busbars.

Click to expand...

If this is the TOP side, then you previously showed us the PCB upside down.
And those capacitor are nowhere to find in your schematics! (Or I´m blind)

Again: many pieces of GND do not give the same quality as one solid layer.

150A??? How? In post#1 you talked about 3A. Why now 150A???

Klaus

KlausST said:

If this is the TOP side, then you previously showed us the PCB upside down.

Click to expand...

Yes, sorry about confusion, they are above schematic as i didn't think they were relevant to PSU. They are not soldered on test boards anyways. But I do have to work around them.

This is how ground plane on bottom side looks like:


And this is top side ground plane. I think it is pretty solid overall (but I could be wrong).

Zac1 said:

And this is top side ground plane. I think it is pretty solid overall (but I could be wrong).

Click to expand...

Solid means solid. A solid rectangle. A solid sheet of copper. No additional traces, no splits, no empty spaces...
Your "plane" is no plane. They are connected fragments. Don´t get me wrong: I don´t want to annoy you and for sure the big copper areas bring some benefit against "simple traces" ... but not that much benefit as you might think. Neither for DC currents nor for HF.
95% of your (stiching) vias are in areas where there will be no current flow. No current flow --> useless.
--> Place your vias where they are needed, where you expect current flow.

For "not that experienced PCB designers" the easiest to follow recommendation for a good layout is to use one completely solid layer.

Later ... The more experience you gain, the more you understand where will be current flow ... Thus with more experience you may be able to "cut your GND_Plane" into pieces without losing performance.

Your layout:
The hole in GND copper (blue) around Q5 acts as an antenna. the bigger the area the lower the frequency and the more prone to pick up frequencies.
Then it is enclosed by a copper loop, creating a high Q resonance. No matter how many vias you are using, as long as the hole is "open" you get this resonance problem.
So regarding this antenna ond resonance it would be better to leave the copper ring around "unclosed". But you should have some experience to find out where´s the best location to "open the loop".
Additionally your power current flow

My opinion with your GND_plane may sound harsh ... but it´s not meant offending. It is meant to be focussed on the application´s failure problem.
Until now we don´t hve enough information to be sure what exactly causes the problem ... but the PCB layout MAY be one of your problems.
And I try to sensitize you on this problem in a way that your future projects start with a true solid GND plane ... to be sure to exclude this problem from the beginning.
--> One problem less to cure.

Klaus

No

I saw 160 V on the result of modifying his LTSPICE file and measured power (Alt+Click) without thinking/knowing yet what were the design specs for the output.
It's should be 12V.

Then I thought why bother stressing a high side switch when a low side switch could be ramped up much easier. Ground is wherever you choose as 0V.

KlausST said:

but not that much benefit as you might think.

Click to expand...

They are mostly to help the current flow from/to big caps.

KlausST said:

Place your vias where they are needed, where you expect current flow.

Click to expand...

maybe this view can convince you:


One thing that may not be obvious from this design is that vast majority of current will flow from/to bulk capacitors, reaching 150A (up to 168V)
DCDC is just a tiny droplet that is meant to sip a bit of power (up to lets say 5W), its stability isn't even that important as making sure Phase mosfets gets full power.

Unfortunately due to size/design constraints I cannot design perfect PCB, I have to work with what i got. And i need to make the "cutout" on the top due to screws/busbars.

KlausST said:

The hole in GND copper (blue) around Q5 acts as an antenna.

Click to expand...

Which hole are we talking about?

KlausST said:

My opinion with your GND_plane may sound harsh ... but it´s not meant offending. It is meant to be focussed on the application´s failure problem.
Until now we don´t hve enough information to be sure what exactly causes the problem

Click to expand...

That is fine, I'm not offended, I know this design is subpar, if I had some tested solution I would take it but so far after couple of months of research i have yet to find something that fits design constraints and I will try whatever I can.

So far I have tested 3 "floaty" designs (unstable), flyback (way too big) and this "classic" DCDC which so far works the best.

I guess i should just order PCB + components again, try to record what happens on boot, and if problem persists come back and try more troubleshooting.
Hoping new ones won't burn as fast.

I would work on your simulation of diode and FET Cdg capacitance with better parts and simulate the failures.

Ctrl+ click for power plots on selected part after adding a plot plane then select it.

D.A.(Tony)Stewart said:

I would work on your simulation of diode and FET Cdg capacitance with better parts and simulate the failures.

Ctrl+ click for power plots on selected part after adding a plot plane then select it.

Click to expand...

I wasn't even able to get this simulation fully working, so unfortunately its beyond my ltspice skills. It works 1/10 times only when i mess up with values in some weird ways.

If every passive part is real, it works better.

It would be prudent to have a fuse feeding the buck mosfet.

also diode 1): https://www.vishay.com/docs/88588/es2f.pdf

2): https://www.vishay.com/docs/88580/egl34.pdf
300V 1A MELF

D.A.(Tony)Stewart said:

If every passive part is real, it works better.

Click to expand...

Indeed, I measured C2 C7, C6, output battery caps with ESR meter (unfortunately it goes only up to 100kHz) and i am finally getting something useful.

Unfortunately simulation is still painfully slow, good news is that soft start and DTC seems to work fine

With zener:


It looks a bit unrealistic but maybe I am wrong?

At 100V overshoot it a lot smaller, attaching sim files (this time its named TL494dcdc.asc)

Easy peasy said:

It would be prudent to have a fuse feeding the buck mosfet.

also diode 1): https://www.vishay.com/docs/88588/es2f.pdf

2): https://www.vishay.com/docs/88580/egl34.pdf
300V 1A MELF

Click to expand...

I am sorry but i do not understand what do you propose, should have probably mentioned english is not my first language so i get confused with english technical terms.