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Title: Formality Synthesis to SCAN: Verification Issue

mini9136

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"I accidentally posted in the wrong board, and I don't know how to delete it. I apologize for reposting it here."

Title: Formality Synthesis to SCAN: Verification Issue

Hi, this is my first post!

I’m running Formality to perform synthesis for SCAN.
The MATCH step completes successfully, but during the Verification stage, Formality keeps running and doesn’t stop.

This issue only happens on my computer with this specific netlist.
On other computers, the same netlist finishes verification without any issues.

Additionally, both I and others are using the same formal.tcl script and running the same commands.

Does anyone have suggestions on what might be causing this?
 

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