Tips for transistor matching in differential amplifier

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Syukri

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Hi...I'm the new guy here,

In my bach. thesis paper one of the design I have to make is to design the layout of Diffrential Amplifier...I've found out that the transistor mathing is important in order to get good output. Can I get any tips....

Furthremore, in Layout geometrical design technique, how do I get a low power consumption design for Op-Amp. Can I just use large area of poly
 

Re: Transistor matching?

The transistor matching is nicely given in Art of Analog Layout book by Alan Hasting.
 

Re: Transistor matching?

Syukri,

1. At schematic level, tie the bulk of NMOS transistors of twin CE to the common ground.
2. In the layout, check to see if the NMOS transistors are placed in the same well, sharing the same diffusion/doping/active layer.
3. Check also that the active load (current source) is symmtrical and the poly-Si connections are parallel and equal between active load and NMOS transistors.

To reduce power consumption,
1. reduce the aspect ration of matching transistors, i.e. decrease W since L is fixed.
2. add poly-Si resistor, each between the source of NMOS and the common CE tail node.
3. add current sink, reduce aspect ratio of active load. decrease W.
 

Re: Transistor matching?

SkyHigh,

reducing W of transitors for given L only worsen the matching as it depends on 1/sqrt(W.L)

Anyway, but only for current sources, increasing W does not increase current consumption. Even more, this make transistors to go more into weak inversio, which for differential pairs increase gm and then matching.

Also, can you explain the effect of connecting the source of transistors to the CE by means of a poly stripe?
 

Transistor matching?

Thanks a lot guy's....
Anyway the sizing of the poly line that i mean before is that in drawing layout, the minimum size of poly is 2λ, I meant it by increasing the λ
 

Transistor matching?

1. you can read some layout books
2. You can enlarge sizes of transistors for matching and deceasing λ(channel length modulation effect), however your circuit will suffer from the increasing of parastic effects.
 

Re: Transistor matching?

Hi

I would recommend using dummy transistors for the input pair the currentmirror
and the currentsource. Take care about the metaldensity being equal over
the transistors. Spend a bit more overlap for the wells to reduce the well proximitiy
effect. Design the transistors in a way that the current direction is in the same
direction. That should give good silicon results

Greetings

Andi
 

Re: Transistor matching?

If I may add something else. Common centroid is the way to go adding what the others told you. IF you need the smallest input offset and the best matching( even better than the normal common centroid) there is even a better way to do it. It's called second order common centroid

regards
 

Re: Transistor matching?

1)
"second order common centroid"
Could we have more informations?

2)
"dummy transistors for the input pair"
Again, you don't need dummies on input pair as long as you are doing a common centroid.

Franck.
 

Re: Transistor matching?

franck said:
1)
"second order common centroid"
Could we have more informations?

2)
"dummy transistors for the input pair"
Again, you don't need dummies on input pair as long as you are doing a common centroid.

Franck.
Click to expand...

Agree with point 2. As for the "second order common centroid"
_ A B _
B A B A
_ A B_

regards
cretu
 

Re: Transistor matching?


As in your statement, to increase W will impose transistor more near weak inversion
and sub-threshold. In this region, the transistor matching is worse. So, based on this
point of view, reducing W under the same current doesn't worsen the matching
necessarily. Besides higher Vod can ease the mismatch of threshold voltage
in current mirror design.
 

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