Dec 14, 2012 #1 S sun_ray Advanced Member level 3 Joined Oct 3, 2011 Messages 772 Helped 5 Reputation 10 Reaction score 5 Trophy points 1,298 Activity points 6,828 What are all the ways to take care timing violation while doing PnR for FPGA? For example one of the way is to change the RTL. Can you please list down in the same way all the other ways to remove timing violation when violation is found after PnR?
What are all the ways to take care timing violation while doing PnR for FPGA? For example one of the way is to change the RTL. Can you please list down in the same way all the other ways to remove timing violation when violation is found after PnR?