Timing Problem when using bitwise AND for large vertors

[lqson]

Hi,
I need some advices for my RTL design.
Is there any differences about timing performance between these two coding style below?
Does the second coding style have a better timing performance?

1)
wire [511:0] A, B, C;
assign C = A&B;

2)
wire [511:0] A, B, C;
wire [255:0] C1;
assign C1 = A[255:0] & B[255:0];

wire [255:0] C2;
assign C2 = A[511:256] & B[511:256];

assign C = {C2,C1};

Thanks
Son

 

[gurucharapathy]

There should not be any difference, as the 'and' operation is bit to bit i.e { A[511] & B[511], A[510] & B[510] ,........, A[1] & B[1], A[0] & B[0] }

 

[lostinxlation]

Many years ago, the synthesis tool(DC) put a buffer on every assign statement and it would have made some difference in timing, but now a synthesis tool is much more sophisticated and I believe it probably doesn't make difference(but no proof for that).

 

[lqson]

Thank you so much!
I've just moved to ASIC design from FPGA design. Before, I met timing issue with this coding style on FPGA.
So it makes me confuse. Your answer helps me a lot.