vhdltestbench
Newbie level 1
- Joined
- Mar 3, 2013
- Messages
- 1
- Helped
- 0
- Reputation
- 0
- Reaction score
- 0
- Trophy points
- 1,281
- Activity points
- 1,288
Hello,
I am triying to simulate fir low pass filter in vhdl test bench, I get square waves from matlab as txt document, and I use ip cores for filter which I produced in matlab in fdatool. I am using text-io in the testbech.
I have two questions
1-Square wave is 100Hz but in txt there are only -1s and 1s. In this filter input port is 16 bit(d_in) . How can I give these -1s and 1s to this input port (d_in)?
2-How can I utalize the clock frequency and sampling frequency so that I can handle and filter different frequency signals?
I am triying to simulate fir low pass filter in vhdl test bench, I get square waves from matlab as txt document, and I use ip cores for filter which I produced in matlab in fdatool. I am using text-io in the testbech.
I have two questions
1-Square wave is 100Hz but in txt there are only -1s and 1s. In this filter input port is 16 bit(d_in) . How can I give these -1s and 1s to this input port (d_in)?
2-How can I utalize the clock frequency and sampling frequency so that I can handle and filter different frequency signals?