timing model for analog blocks

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rakko

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i have a chip with some analog blocks and some digital. i want to do STA on the digital blocks but 1st need to generate a timing model for all analog blocks. how can i generate timing model (stamp?) for an analog block which is good enough for primetime static timing analysis.
 

I expire the answer about the question?
If you have some information about mixed-sginal design, could you give me some for study and discuss each other?
melonpy@163.com
thanks!
 

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