Timing issue in verilog design?

[Dharam7]

I have designed a verilog code for a DSP algorithm using xilinx vivado 2019.2. The algorithm can process 1000 samples at a time as shown in attached figure. It took 10 ms to process 1000 samples (tested seperately only for 1000 samples). My aim is to process 3*1000 data samples and I have modified the code. When i=1, it will process all the samples of A1…A1000 and stored in a RAM. When i=2, the algorithm selects B1…B1000 and process all the data and added with the stored value in the RAM. Similarly, after i=3 same steps are repeated and added with the stored value in the RAM and finally got the output.
Although for 1*1000 samples algorithm was taking 10 ms to process them. But after using 3*1000 data also the algorithm is taking 10 mili second to complete the process. So, am I getting the correct timing result of 10 ms for processing of 3*1000 data.

 

[KlausST]

Hi,

I´m no specialist in this field.
But as far as I understand... when you set 1, 2 or 3 x 1000 then there are 1, 2 or 3 parallel processes.
this is nothing special for an FPGA.Thus regardless whether there are 1, 2 or 3 parallel processes it will take the same time to process your 1000 items.

--> It is hardware that can (and does) process a lot of signals in parallel.
It is no softtware that processes command after command.

Klaus

 

[TrickyDicky]

I dont get what you're asking for - do you have a problem you want help with?