Timing diagram from VHDL clock divider code

Code VHDL - [expand]
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library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 
use IEEE.STD_LOGIC_UNSIGNED.ALL; 
 
entity MIDTERM2 is 
 port(CLK : in STD_LOGIC; 
 ACLR_L : in STD_LOGIC; 
 SIGOUT : out STD_LOGIC); 
end Midterm2; 
 
architecture prob1 of MIDTERM2 is 
signal Strobe, IntNet : STD_LOGIC; 
signal Hardware : STD_LOGIC_VECTOR(1 downto 0); 
signal aclr : STD_LOGIC; 
 
begin 
 aclr <= not ACLR_L; 
 SIGOUT <= IntNet; 
 Strobe <= ‘1’ when Hardware = “10” else ‘0’; 
 
 process(CLK, aclr) begin 
 if(aclr = ‘1’) then 
 Hardware <= “00”; 
 elsif(CLK’event and CLK = ‘1’) then 
 if(Strobe = ‘1’) then 
 Hardware <= “00”; 
 else 
 Hardware <= Hardware + 1; 
 end if; 
 end if; 
 end process; 
 
 process(CLK, aclr) begin 
 if(aclr = ‘1’) then 
 IntNet <= ‘0’; 
 elsif(CLK’event and CLK = ‘1’) then 
 IntNet <= Strobe; 
 end if; 
 end process; 
end prob1;