hi cmos babe,
1. Why timing constraint is important?
ans: to make sure ur design can meet the target spec (usually target frequency). In another words, no timing violations.
2. can a design work without them?
ans: No.
3. what's the starting point of understanding all these timing stuff, what are the main constraints that I should know well .
ans: In my opinion, lecture notes and books on timing analysis are the best starting point. Then, u need to get ur hands on the design. Write a small design (verilog/vhdl or gate, up to u), synthesize and perform timing analysis. Read the timing report and analyze. Try to understand from the timing report and if u faced any probs u can discuss in this group or ask from experience dude in ur company.
The main constraints are clock, input delay and output delay perhaps loads and drive strength too.
4. is there a step by step approach that I can follow to be sure that no hold/setup violations will occur?
ans: This advice was told to me by an experience dude (a good friend of mine) during my first experience in FPGA design. I still ask these Qs to myself even ASIC design.
1. check all the clock constraints (if u have multiple clocks)
2. how the fsm implemented?
-> if can, use one-hot encoding
3. how about the fan-out?
4. have u set limits on the fan-out?
-> large capacitance may mess up
5. how about the architecture level?
After asking these Qs to urself, moving to the physical level would be warranted.
Therefore, all these are only a small contribution from an intermediate engineer
. Please do give comments &/ suggestions. Anyway, we all still learning and it will not never stop.
Good luck and enjoy
-no_mad