timing constraints for 2:1 or 1:1 clock ratio during synthesis and STA

Hello, everyone~

In my digital design, there are two modes for configuring operation clock frequency.

[mode 1] CPU:300MHz, Bus:150MHz (2:1 mode)
[mode 2] CPU:180MHz, Bus:180MHz (1:1 mode)

As you see, the worst case of CPU is 300MHz, and the worst case of Bus is 180MHz.

But, I can not give clock period of 300MHz/180MHz to my Design Compiler and Prime Time
because only 2:1 or 1:1 clock ratio is available in my design.

In this case, how should I give timing constraints to my synthesis(Design Compiler) and STA(Prime Time)?

It's better for you to prepare two timing constraints ( common part and specific part ) for each scenarios.
After that, MCMM ( Multi-corner multi-mode ) is one of the way for your purpose.
But for PrimeTime, you can analyze each timing respectively. One for 2:1 mode and the other for 1:1 mode.

gomlife330 said:

Hello, everyone~

In my digital design, there are two modes for configuring operation clock frequency.

[mode 1] CPU:300MHz, Bus:150MHz (2:1 mode)
[mode 2] CPU:180MHz, Bus:180MHz (1:1 mode)

As you see, the worst case of CPU is 300MHz, and the worst case of Bus is 180MHz.

But, I can not give clock period of 300MHz/180MHz to my Design Compiler and Prime Time
because only 2:1 or 1:1 clock ratio is available in my design.

In this case, how should I give timing constraints to my synthesis(Design Compiler) and STA(Prime Time)?

Click to expand...

Hi,

In one mode itself you can do it by creating all the four clocks CPU (300MHz, 180MHz) and BUS (150MHz, 180MHz).

You can create two clocks on single port using "-add" option. So, create CPU 300MHz and CPU 180MHz clock on same clock port with "-add" option to "create_clock" command . Similarly you can do for the BUS clock also.

Provide a logical exclusive clock relationship between CPU 180MHz and CPU 300MHz clock. So, that tool will not try to do timing between these two clocks as these two clocks will not be present in a single mode. Similarly for the BUS clocks as well.

You need to provide addition logically exclusive constraints between
1) CPU 180MHz clock and BUS 150MHz clock
2) CPU 300MHz clock and BUS 180MHz clock

Hope this can help you...