Hi,
I agree with Barry.
I´m no expert in this - so please experts correct me if I´m wrong.
As far as I understand it: The constraint is common for all data lines. But for me it seems you want to do an individual constraint for each data line.
You rather add meanders on the PCB to meet the timing of the datalines.
And I recommend to treat the clock signal from routing and trace length equally than the data lines (unless there is a dedicated approach that contradicts this)
Now the ADC datasheet tells you how much delay you can expect from rising_clock to data_out.
If you treat signals and clock equally this gives the information for your FPGA timing constraint. Consider worst case.
You may expect a signal speed of about 150mm per nanosecond.
But if all signals are treated equally the absolute delay does not matter at all.
I recommend to use paper and pencil and draw a realistic timing diagram of your signals.
Then you add worst case timings. This shows you whether it´s better (what results in better margins) to use the rising or the falling edge to latch_in the signals at the FPGA.
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Just a remark. Your sketch shows a 120MHz clock that directly clocks out 12 data lines. And you say these are single ended CMOS signals. This is quite a high data rate for single ended CMOS signals. Can you please confirm that I understood correctly.
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If you need more detailed assistance then you need to give the timing of the ADC and the PCB layout. So we can do some realistic calculations and give recommendations.
Klaus