Timing and routing to large number of memory banks

[BigKuma]

I am using Quartus and Stratix V.

I have a design that has 14 memory banks. Each bank is 64xM20K blocks.

There is block (MUX) that reads/writes one bank, while another block (FFT) that reads/writes another bank.
There is a 1 to 14 registered router between the blocks and memories.

The clock speed is 180Mhz.
I am getting setup errors on read and write inputs to this memory from the registered router.
Depending on the build, -.5ns to -1.5ns.

My initial idea was to give the tool more registers between the router and memories. I double registered each of the 14 memories’ input and outputs.
(The latency is not important in my design)
When I look at final placement, all my extra registers got placed next to the router, and not somewhere half way between router and memories.

The router and memories are in the same vhdl file. But MUX and FFT are outside blocks.

Initially, the M20K usage was up to 99%. I brought it down to 82%, and I still see the same errors.
What do you recommend that I do to have my extra router registers be placed ½ way between router and memories ?

Thanks,
Mark

 

[ads-ee]

Use regional constraints on the set of registers that connect directly to the M20K blocks. As I don't know the general architecture of your design or if there are any common signals that go to the registers, I can't make many suggestions on what may be causing the placement issue.

If there is combonational logic following the added registers that is part of the memory/router design then that might be causing the issue as there may be no good placement for the registers if they end up having to connect to multiple memories due to the combonational logic cones. If something like this is going on you could try enabling retiming during synthesis (I'm pretty sure Quartus has that capability).

 

[TrickyDicky]

Getting signals into and out of rams has a timing penalty. If you have large inter-dependent rams the sources of these signals may be a long way from the ram that requires it. You may need extra and duplicated registers to try and minimise the routes to the ram.

 

[BigKuma]

The signals from router to the memories are all separate and registered.
Even in the timing report, I see only two entries in the path, WR_ADDR_REG(my signal) and asyncram address register.

There may need to be internal duplication required, but I can't control it. Each bank is 64 M20K blocks, but at at my abstraction level, it's just a single memory with read address, write address, data lines, etc.

I know it's some sort of a failure on Altera crew, since I just turned up the routing effort to 1.5, and after 5.5h of build time (normally 4h) that timing error went away.