Timing analysis on a design and deciding its maximum operating frequency ?

[hcu]

Hello all,


I am doing synthesis and implementation on a vcu108 FPGA board with a vivado tool.

case 1: my constraint for the clock is 10 ns. here i get slack as 0.7 positive slack and a 0.025 positive hold slack. And a dialogue "timing constraints are met" is shown. From this i can say the maximum operating freq of this design is around 107 mhz.

case 2 : when i change the clock constraint to 4.0 ns. here i got a slack of -1.580 negative and a 0.032 positive hold slack. And a dialogue "timing constraints are not met" is shown. one can see a calculated fmax on paper is 180 mhz.

why both analysis not concluding to the same fmax. number ?? Is it because of consideration of different paths at different runs. ??

 

[TrickyDicky]

The fitter will use the timing constraints during fit, and if the constraints are not met it will try and work harder to meet timing. So once it has met timing, it will generally stop.
Usually, it is not the FMax that people design by, it is the frequency of the interfaces required to get a specific bandwidth.
Eg - if you have a 10G ethernet interface, you will need a 64bit data bus running at at least 157Mhz to service the data rate, or 128bus bus at 79Mhz

This is what usually determines your clock requirements.

 

[hcu]

The fitter will use the timing constraints during fit, and if the constraints are not met it will try and work harder to meet timing. So once it has met timing, it will generally stop.
Usually, it is not the FMax that people design by, it is the frequency of the interfaces required to get a specific bandwidth.
Eg - if you have a 10G ethernet interface, you will need a 64bit data bus running at at least 157Mhz to service the data rate, or 128bus bus at 79Mhz

This is what usually determines your clock requirements.

Thanks,
so, can i say this, In case1 fitter has reached its goal with minimal effort ,but it has a scope to do a better job .
Now coming to case 2, it got failed even after working so hard hence we can conclude fmax can be upto 180 mhz atleast from the case2.
what you think ?

 

[TrickyDicky]

1. The "better job" is subjective. It met the specifications you required.
2. Yes. This design should work at 180MHz. FOR THIS BUILD. On each change on source code or fit seed you might get better results. So there might be another result with > 180Mhz.

Fitters generally use Modelled Annealing (https://en.wikipedia.org/wiki/Simulated_annealing) for fit results. On that wiki link, from the first temperature graph - if you consider the X axis as all the seed start points, and the Y axis as the best fit time (lower being better), then you'll see the fitter can get caught in a low or high trough, depending on the seed. Altera released a paper on it 7 years ago:

**broken link removed**