Timing Analysis of Post Layout designs...

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giggs11

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Hii,

Static timing analysis is performed to inspect the delays of the paths. I also noticed in several design flows that post-layout timing analysis is also done as part of the verification process.

I have done STA using Primetime but how does one perform post layout timing analysis using Primetime or is it even possible in the first place..?

Thanks.
 

Hi giggs11:

You should do STA before and after layout.

We use PT for gate-level pose-layout STA, you can sign-off it. If you

wanna do circuit-level STA, PATHMILL will be the tool.

You can do gate-level pose-layout STA with Gate-level netlist, SDF and

RC from lauout guys offer you. Remeber, after layout, the CT is real, so

you should modify you clock constrains.
 

hi,
if your deisgn is under 0.25um, so it's better to use primetime-si to signoff or use cadence tools such as celtic/cte/voltagestorm/signalstrom.
they are also signoff tools.
 

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