encounterä¸timing analysis
Hi Johnson,
Could you clear up following:
1.what is the "dual-edge" triggered flops. is it the same flop can be triggered as leading edge so, as trailing edge of the same clock pulse? Or, is your design contains both kinds of flops (some flops are triggered by leading edge, another flops are triggered by trailing edge)?
I am afraid I've ever faced a flop is triggered by both-edge in the same time
2. Encounter CTE "supports" pulsed latches. A CTE STA report looks like CTE considers pulsed latches as regular flip-flops. But, I am not able to look at the liberty file right now to check how pulsed latches were coded (perhaps they were coded as a regular flops).
Does anybody know more about it?