Timing Analysis in Cadence Encounter

[Johnson]

pulsed latch liberty

Without bothering each other with old question "synopsys is better or cadence", is it possible to start a simple project with cadence encounter from RTL and finish in GDSII without the need to switch to synopsys tools? In cadenec flow which tool is responsible for timing analysis? or which cadence tool is counterpart of primetime?

 

[kulyapinav]

what is the latest version of cadence encounter

Cadence Timing Engine named CTE (common timing engine). This engine is built in SOC Encounter platform. Besides, CTE is allowed as stand alone tool that is named ETS (Encounter Timing System). So, If you have SoC Encounter license pack you can use CTE through the same Encounter Shell/GUI where you make P&R. Just use 'timeDesign' command for STA and 'optDesign' command for timing optimization.
Look at brief demo about Encounter GUI based STA:
https://www10.edacafe.com/video/display_media.php?link_id_display=26114

 

[kumar_eee]

cadence encounter

It is possible.. But the industries are still using PrimeTime as a sign off tool.. Refer "Timing Analysis Commands" chapter in Encounter Text Command Reference Manual..

 

[navneetgupta]

cadence timing analysis

I agree with kumar_eee.
PrimeTime is the most popular tool in industry for TA.

 

[Johnson]

cadence encounter sta

I had two questions and want to repeat them here again:

1) Regarding dual-edge triggered flip-flop, is cadende tools and STA engine supporting this kind of flip-flops? what about synopsys flow and tools?

3) Is current digital design tools supporting pulsed latches? I heard thet magma is supporting it, but I do not know is it the case for cadence and synopsys flow?

Added after 4 minutes:

Look at brief demo about Encounter GUI based STA:
https://www10.edacafe.com/video/display_media.php?link_id_display=26114

Is there any possibility to save these tutorials?

 

[kulyapinav]

encounter中timing analysis

Hi Johnson,
Could you clear up following:
1.what is the "dual-edge" triggered flops. is it the same flop can be triggered as leading edge so, as trailing edge of the same clock pulse? Or, is your design contains both kinds of flops (some flops are triggered by leading edge, another flops are triggered by trailing edge)?
I am afraid I've ever faced a flop is triggered by both-edge in the same time

2. Encounter CTE "supports" pulsed latches. A CTE STA report looks like CTE considers pulsed latches as regular flip-flops. But, I am not able to look at the liberty file right now to check how pulsed latches were coded (perhaps they were coded as a regular flops).

Does anybody know more about it?

 

[Johnson]

With dual-edge triggered flip-flop (DETFF), I do mean a flip-flop which is able to capture data at both clock edge, i.e. rising and falling. The DETFF is able to do the same job with half of freq. compared to ordinary flops.

 

[kulyapinav]

Hi,
I found "pulsed latch usage"_vs_STA paradigm:
latches have similar timing libraries to that of conventional flops. That is the reason why I saw Encounter STA reports with pulsed latch design are exactly the same as those with edge triggered flops. It should work fine for setup timing analysis, in my mind. But, hold timing analysis must take special care

 

[Johnson]

With dual-edge triggered flip-flop (DETFF), I do mean a flip-flop which is able to capture data at both clock edge, i.e. rising and falling. The DETFF is able to do the same job with half of freq. compared to ordinary flops.

Any comment?

 

[kulyapinav]

Hi,
Sorry, I've ever used dual-edge flops in my designs. I am pretty sure Cadence SOC design flow supports such flops, SOC Encounter is one of two leaders ... and supports most of Liberty Extentions, but you should use SOC Encounter version >=7.1.

 

[Johnson]

So can we conclude that pulsed dual edge triggered latch is now supported with major EDA vendors, specially cadence soc encounter 8.1?

 

[kulyapinav]

Hi,
Yes, You can. If pulsed latches have similar timing libraries to that of conventional fip-flops