timing analysis does not meet

Hi all

I have 2 problems in meeting timing analysis....(I am using Xilinx ISE 13.2)

First of all, it does not meet the timing, I had the timing requirement of 1.5ns which does not meet since the setup time slack was -0.68ns. Note that I am having the following error

Slack (setup path): -0.668ns (requirement - (data path - clock path skew + uncertainty))
Source: sip_mig_ddr3_512MB_fifo_1/i_ddr2_fifo/i_ddr3_mmu/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[15].u_iob_dq/u_oserdes_dq (FF)
Destination: sip_mig_ddr3_512MB_fifo_1/i_ddr2_fifo/i_ddr3_mmu/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[15].u_iob_dq/u_iserdes_dq (FF)
Requirement: 1.500ns
Data Path Delay: 2.297ns (Levels of Logic = 1)(Component delays alone exceeds constraint)
Clock Path Skew: 0.187ns (2.203 - 2.016)
Source Clock: sip_clkrst_fm680_0_clkout_clkout<5> rising at 0.000ns
Destination Clock: sip_clkrst_fm680_0_clkout_clkout<17> falling at 1.500ns
Clock Uncertainty: 0.058ns

Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Discrete Jitter (DJ): 0.091ns
Phase Error (PE): 0.000ns

Click to expand...

Note that the errors occured at the dq pin connection from FPGA to DDR3 hence it is designed by the MIG from Xilinx Logcore software...hence I have no authority to change it.

But as measure from my side, what I did was to change the parameters of the MAP properties such that:

Changed the Global Optimization to Speed

The purpose was to increase the optimization. Hence now I am getting this error,

ERROR:ConstraintSystem:300 - In file: fm680_ggeen_lx240t.pcf(48492): Unexpected end of file '.\fm680_ggeen_lx240t.pcf' during read.
ERRORar:51 - The .pcf file contains errors. PAR cannot proceed.

Click to expand...

I cannot understand how to remove this error. Is the .pcf file really important. then I ran the following command using command interface hence there was not error, but I am not convinced since I am not properly aware of the .pcf file function in this circumstance since I never created this file myself

par -w -intstyle ise -ol high -xe n -mt 4 fm680_ggeen_lx240t_map.ncd fm680_ggeen_lx240t.ncd

Click to expand...

Later I ran the timing analysis and found the same error

ConstraintSystem:300 - In file: D:\Coding\4dsp programs\219_fm680_ggeen\output\fm680_ggeen_lx240t\fm680_ggeen_lx240t.pcf(48492): Unexpected end of file 'D:\Coding\4dsp programs\219_fm680_ggeen\output\fm680_ggeen_lx240t\fm680_ggeen_lx240t.pcf' during read.

Click to expand...

Do a "Clean project files" and then rerun? Older versions of ISE sometimes got confuzzled like that after changing settings.

This might be an older version of mig. You shouldn't have a 680M clock in the design except for the fast clock of the oserdes. The logic should be running at 340MHz with a 4:1 serdes -- 4b per 340M cycle being the same as 2b per 680M cycle. Possibly even 170MHz with an 8:1 serdes.

permute said:

This might be an older version of mig. You shouldn't have a 680M clock in the design except for the fast clock of the oserdes. The logic should be running at 340MHz with a 4:1 serdes -- 4b per 340M cycle being the same as 2b per 680M cycle. Possibly even 170MHz with an 8:1 serdes.

Click to expand...

thank you
this might look the case since is is the older version of MIG design which I am trying to fabricate since the vendor their own design and I am trying to just fit my design in this...

but unfortunately I could not completely understand what you said, can you refer some of the reading material. have read about oserdes and iserdes but never met this case. Also could not find this in the MIG specification.

A requirement of 1.5 ns did have me wondering what fpga you were using...

1.5ns is very high speed,i don't think xilinx has FPGAs which supports this much speed on DDR3 interface..Are u sure that ur going to operate the memory at 1333Mbps data rate? or is it 666Mbps data rate?

mrflibble said:

A requirement of 1.5 ns did have me wondering what fpga you were using...

Click to expand...

Virtex-6.
I will recheck the timing things again...

sivamani said:

1.5ns is very high speed,i don't think xilinx has FPGAs which supports this much speed on DDR3 interface..Are u sure that ur going to operate the memory at 1333Mbps data rate? or is it 666Mbps data rate?

Click to expand...

hi virtex-6 supports DDR3 with such high speeds... I am trying to study the data sheets meanwhile, I found in the ds152 from xilinx the following chart attached. according to it the buffers support upto 700 MHZ. I am using virtex-6 XC6VLX240T speed grade -1

I have tried hard to resolve the problem, but the thing is that the errors are

1. setup error inside the MIG design, more specifically, inside the phy block of mig design and as an example one of them has source
ISERDES and destination as OSERDES.

2. second, I cannot find any relation to it in the ucf file and then in the actual error...


HOW CAN I IMPROVE THE SETUP ERROR...
HOW HOW HOW

what to do in the VHDL code...give advices... and see the figures as well

Make sure you have all of the UCF constraints from the example design (modified appropriately for hierarchy names). MIG has historically had some 90d clock to div-clock paths that can be relaxed. Likewise, MIG has had LOC constraints for some elements that can only meet timing if they are placed in ideal locations.

hi again


can you share with me how can I relax the MMCM created constraints?
I mean the constraints that the MMCM generate ?

I am trying to relax it but cannot using TIG, we need to do instantiation or what?

you can't reach those speeds with the part you are using.

aruipksni said:

you can't reach those speeds with the part you are using.

Click to expand...

I have shown above that it is possible for communication with DDR3. virtex-6 communicates with DDR3 and 1.5 ns is the communication speed of DDR3. What else should I tell to convince. I also have attached the image from virtex-6 data sheet in above replies somewhere.

can you share with me how can I relax the MMCM created constraints?
I mean the constraints that the MMCM generate ?

I am trying to relax it but cannot using TIG, we need to do instantiation or what

Click to expand...

ok that was really easy, I was missing a little thing.

Now my question is. Will ignoring the timing path actually help or not?
By doing so the error is of course not there. But it means we are ignoring the potential errored path...
please reply.

syedshan said:

ok that was really easy, I was missing a little thing.

Click to expand...

In the interest of helping future readers of this thread, what little thing did you need to fix?


As for the TIG constraint ... if it hurts or helps really depends on the exact thing you are applying the TIG to. Sorry if that is a little vague.

I use TIG when I am pretty sure a certain timing contraint is not needed or doesn't make sense. Or sometimes to some FIFO paths when there's a known issue, that sort of thing.

What you can do is use the TIG constraint, and then inspect the post PAR result to see if it "looks sensible". Not a 100% certain method, but it does help in getting an idea. Certainly better than being stuck in your project.

I suppose you are using soft IP of DDR3. Is your design utilization high? High utilization might cause the soft IP to fail timing due to congestion at place & route stage.
I seldom use Xilinx but I know Altera has a feature of "logiclock". If there is similar feature in ISE, perhaps you can try it out.