[SOLVED] Timing analysis Cadence RTL compiler

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Hi all

I want to do some post synthesis analysis using Cadence RTL compiler to understand the timing concepts.

While doing this i got into a doubt that is what will happen if i define clock only for the clk port and keep other ports undefined like not setting any input or output external delays.

By doing like the above.. how rtl compiler generates timing report and i saw R and F in the timing report of a synthesized design.

What does this R and F stands for?

thanks.
 

If you don't specify the input and output delays, then the setup and hold analysis for the flops at the periphery of your design will be very optimistic.
R and F stands for rise and fall. You will come across them in your timing report for a selected path.
 
If you don't specify the input port delays, then the tool will analyze properly only the register to register paths within the clock domain. The timing report has paths
a) input to register --> this will not be done properly.
b) register to register
c) register to output
d) input to output ( combinationals ) --> this will not be done properly
 
hi
thanks for the comments.

R and F stands for rise and fall it is ok.

Then after one instance my arrival time is "Tr" R and another instance arrival time is "Tr1" F so how it changes R and F through the path.

thanks.
 

It depends on whether the signal is changing from 0 to 1 or 1 to 0. In the earlier case it shows as R while in the latter case it shows as F.
 
Still i am unclear of R and F notations.. let me give an example..

Let us assume a D flipflop which works on positive edge of a clock,
i write a simple sdc command of clk1 of 20ns period of 50% dutycylce.
and i synthesized and report the timing.. that time i saw that
accu(0)/CK is 0 R (launch)
and
the output accu(0)/Q +161p(delay)(arrival) F
how this F comes in this report.. please give an explanation.


If you are unclear of this cenario please let me know.

thanks
 

"accu(0)/CK is 0 R" means that at 0 time we are considering the rising edge of clock.
"accu(0)/Q +161p(delay)(arrival) F" means that at 161ps (which is the clock to Q delay) we are considering the case when the Q output falls from 1 to 0.
At Q we could have considered the rise also but the delay experienced for the 1 to 0 fall is greater than that experienced during the rise. So we consider the fall.
 

Hi thanks for the explanation..

I also verified using RTL compiler.

But what i found is that, actually the rise delay is more than fall delay but rtl compiler considered the lowest delay and for the same path after a full adder it considers the maximum delay path which is "R" delay.

I am wondered while seeing this. Is there any reason for this. And do you think slew comes into play?

thanks
 

As per my understanding the tool should always consider the maximum delay path because it does not know the status of the signal at any point of time. So in case 1->0 delay is grater than 0->1 delay, it should always choose 1->0 delay. The timing path that you see reported by primetime always considers the worst case delays.
It also depends whether you are doing setup analysis or hold analysis.
Skew should not matter in this decision. If skew is present, then the arrival time at the capture flop will change. It will not be one period. It will be less or more. So skew is considered here.
 

Hi

While analysing the worst path i just noted that .. for a port acc[0]->q
there are two delays input delay and output delay.

Input delay R: 189p F: 161p
output dealy R: 1402p F 1642p

Output delay is more for the fall and

I know about input delay and what is meant by output delay.. and i presume it chose the fall input delay of 161p by the output delay of falling edge.

please explain about the output delay at the pin.

thanks
 

I suppose it must be a flop at the input interface of the design from an input port. Input ports usually have input delays associated with them and not output delays. So it has chosen the input delay.
 

yes of course i am having a flip-flop at the input.. and it takes the fall delay because the combinational elements after the flipflop
causes more delay for the falling edge. and again at hte final flipflop produces more delay for the rising edge so that my compiler chose fall after the first flip flop.

But i want to know what is the output delay? it is actually opposite to the input delay. i know the definition i think the output delay is calculated form the lib file. am i right?

thanks
 

The output delay is not calculated from the lib file. The lib file will give delays of gates. Using gate delays, setup and hold times,wire delay we have to calculate the output delay.
The output delay is for output ports like the input delay which is for input ports. You need to understand it with the help of a timing diagram. That will make things clear.
 

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