set time violation must be fixed in the pre-layout stage,or u would get a fail design!!
slightly hold time violation can be fixed in the post-layout stage.
best regards
Athur
Thanks everone
"if u have 10% timing violation, use synthesis approach, if you have more , redesign the violated part may be good"
as said by funzero
is tht 10% with respect to total number of paths?
or somethingf else
10% is the percentage of the timing by which your worst path is failing.
For example, if you are working on 100Mhz(i.e 10ns clock period), and your worst path is more than 11ns, which is 10ns(allowed) + 10% of 10ns
Kr,
Avi http://www.vlsiip.com