Time slot in Verilog?

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davyzhu

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Hi all,

When reading Verilog article, I am confused with time slot idea.

For example, a non-blocking assignment,
@(posedge clk) DOUT<= #1 DIN;

Will this assignment completed in one time slot or two time slots (Evaluate RHS at 1st time slot; and update LHS of NBA at 2st time slot)?

BTW, is there any article visualize the #delay in Verilog time slot? Thanks!

Best regards,
Davy
 

i think it will
Evaluate RHS at 1st time slot; and update LHS of NBA at 2st time slot
you r right


correct me if i am wrong
 

first, this assignment can not be sythesisd, so we don't use it in our design.
second, this assingment will finished in one time slot if your clock period is longer than 2 timeunit which you definit ahead of your testbench. for instance, if your clock period is 10 ns, this assignment is implemented at 5ns also the posedge of the clk, then the DOUT will be assigned at 6ns for DIN is valid at 5ns.

am i make is clarification
 

This will complete in 2 cycles and will be ignore by Synthesis tool
 

Hi all,

Thanks a lot!

I want to know what the simulator will do and I just use the assignment in testbench (NOT RTL).

I have read some paper about "event regions". And I find non-blocking assignment is executed at NBA state. But I don't know where is non-blocking assignment with #delay executed?

Best regards,
Davy
 

in this all the events in DIN are placed in the queue (when the statement is execute) since it is NBA and it will have the output at every posedge of clk.
 

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    davyzhu

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