Time Interleaved ADC Filtering at Output

[Puppet123]

When making time interleaved ADC you get gain, offset mismatches along with bandwidth and timing mismatch/skew.

How can mismatches be stopped using filtering - how can I simulate this filter using circuit simulation ?

 

[KlausST]

Hi,

Please describe more exactly what's your concern.

Klaus

 

[FvM]

To simulate dynamic mismatch and its possible compensation, you need
1. a mismatch model, e.g. specified as acquisition bandwidth and sampling time skew
2. a hypothetic input signal applied to the ADC pair
3. a compensation filter prototype, e.g. RC or LC low pass

 

[sutapanaki]

In a interleaved ADC you get spurs that are at harmonics of Fs/N, N being the interleave factor. The spurs from gain mismatch, timing skew and bandwidth mismatch are actually at k*Fs/N +/- Fin. So, they depend on you Fin and Fs. In my view it will be difficult to filter out spurs that fall into your signal bandwidth. Usually, people try to match subADCs as much as possible and use calibration for the mismatches.