Time constraint for big project in FPGA, Quartus II/TimeQuest timing analyzer

Hello,
I got problem when trying to do my project. It's quite big with some FFT, Filter ... and so on.
The result signals are some way getting wrong. I thinks it causes of time violation. I tried to read some documents about time constraint. They all talk about registers. But there're many register in my project which I don't know all of them.
My design is divided to some main blocks.
Question, How can I constraint it?
Do I have to constraint a megacore plugin such as FFT, Filters,
Can I consider a bock FFT like a register. So that I can constraint particular block, and then constraint all project?
Thanks you.

timing constraints are all about giving the placement and routing tools knowledge of the required performance of a design. Therefore constraints are almost always about registers...
1. timing between registers inside the part.
2. timing from a pin to a register in the part
3. timing from a register to a pin of the part
4. pin to pin timing (propagation delay for asynchronous paths)

at a minimum you'll need a create_clock constraint to set the required clock period. This gets applied to all register to register paths everywhere in the design. If you have more than one clock you'll have to have multiple constraints.

If you have multiple clocks and they are asynchronous to each other you should add set_clock_groups between the clocks that are asynchronous so the tools won't try to meet timing between clock domains (hopefully you've properly handled clock domain crossings).

Then there are set_input_delay and set_output_delay to deal with pin to register and register to pin timing respectively.

Hello ads_ee, Thanks for your answer.
I still have question that Do I have to care constraint inside blocks FFT, FIR? They are all complicate and generated by mega core function by altera. I don't know their structure.
How can I make sure that these blocks work well, do not violate time requirement?

They internals of megacores will use whatever clock constraints you put on the input clock to the core. All endpoints (i.e. registers) of the clock will be constrained by the period constraint you place on the clock.

Also if the megacore wizard produces any sdc file for the core you better add those constraints to your sdc file.

thanks ads_ee!