threshold voltage vs temperature in MOSFET

[ee484]

gm/id

Hi, all.

I heard that there are folks who use gm/iD methology for analog design circuit (In contrary, Vov or Vdsat design method) - some paper discuss about this methodolgoy (i.e., JSSC 1995)

Are real designers using this methodolgy to design analog blocks?

I understand that you first have to make script to approximate the all the design parameters (i.e., W, gm, iD etc), then later you just tweak the designe a bit based on your parameters.

If real designers use gm/iD methodology, are they using for all analog blocks or just use for big blocks such as opamps?

I'll appreciate if you have examples....

 

[holddreams]

gm id methodology

I have the same problem.
Hope somebody can share his experience.

 

[ee484]

gm id

Where did you learn gm/iD technology?

 

[Humungus]

gm/id methodology

Hi guys,

The gm/Id methodology is an exellent method as it considers with a single set of equations the full possible operating range (from weak to stron inversion). By specifying the gm/Id of a transistor you know in which regime the transistor is operating so you know if the hypoteses you considered in your design are true or not.

Tghe gm/Id method is more useful when you have a good compact model fitted as EKV or ACM to perform sizing scripts.

Another important point is that you can analyse a lot of parameters that depend in a general way of gm/Id. For example the gain of an single-transistor amplifier, known to be

Av=gm/gd
can be expressed as
Av=(gm/Id)Vea (up to you to demonstrat it, very easy)
Vea is the early voltage.

In classical design methods, it is said
gm=2*Id/(Vg-Vth)

Actually this equation considers gm/Id=2/(Vg-Vth). Nevertheless, this equation is only valid in strong inversion and by only considering strong inversion operation you oversize your design (whichever it is).

If, conversely, gm/Id is expressed by a continuous equation (derived from the EKV model, for instance) you can write

gm=(gm/Id)*Id which is always valid.

Also matching can be analyzed interms of gm/Id. For example, the offset of a differential pair it is normally stated as

δVin = δVth + ((Vg-Vth)/2)*δId/Id (this is only valid in stron onversion)

Actually, this should be writen as

δVin = δVth + (id/gm)*δId/Id (valid in all operation ragions)

So you can analyse the full behavior of your circuit in terms of gm/Id

 

[ccw27]

gm id design methodology

In my opinion this methodology is a good way to size the transistors since the long channel equations are no longer accurate. From my experience using gm/id gives a good approximate value when comparing the simulation results with the initial calculation. So I guess less tweaking is necessary.

The long channel equations are still important so you know what parameters need to be tweeked once you are in the simulation phase. To summarize in my opinion a combination of the two are as good as you can get.

Not sure what other people have to say about this. Let me know !! Its an interesting topic to discuss.

 

[ee484]

gm id design

Thanks guys...

It seems that most of people agree on the usefulness of gm/id design methodolgoy. But, I would like to have more solid example if anyone has one.

Thank you...please leave your opinion...please

 

[jutek]

id gm

Tghe gm/Id method is more useful when you have a good compact model fitted as EKV or ACM to perform sizing scripts.

Humungus, could you write what sizing scripts do you mean??

How to plot gm/Id characteristic in HSPICE, what analysis should i perform?
I want to have gm/Id on y axis and Id/(W/L) on x one. I do .dc width start stop step but then the characterisctic is not asexpected

I use a level-49 hspice model, is it suitable for this method?

regards

 

[ee484]

gm/id design methodology

Is there anyone who has experience in designing circuits based on this methodology?

Can you share some experience with us??

 

[dipswitch]

id for gm

Good discussion, hopefully we can have more inputs on this.

My experience is that it is an excellent starting point for circuits; i.e., a good method for feasibility studies, as well as estimations of first pass designs on very new technologies.

For older technologies, it is far better (and almost universally encouraged) to start with a circuit that is already proven on silicon.

 

[nxing]

the gm/id methodology

check berkeley's EE240 course and they taught that during class.

 

[mohazaga]

the gm/id design methodology

Hi ,

Thankx for this valueable discussion , but i try to get the berkeley EE240 course , but I cannot .
So , how to get to learn this methodology in analoge design .
Thanx

 

[ee484]

why use gm/id

gm/iD methodolgy is now developing and some engineers have been using it.
However, there is no single solid method to accomplish design with this method.
I guess you have to learn by thinking and some try and error bases.

I don't have long time experience with Vdsat method (conventional method I believe), however, this gm/iD method seems to require me to think more about circuit performance and design aspects.

Find your own way...I think that is the answer! (You might not like this answer..though -.-

 

[ccw27]

gm/id in hspice

Berkeley EE240 **broken link removed**

Lecture 4 talks about gm/id design. Basically you need to try it yourself and you will find a way to use this methodology.

Stanford EE214 also talks about this methodology. You can search the forum, the lecture is uploaded somewhere. Or you can PM me and I can send you.

Good Luck !

 

[ccw27]

all gm ids

Here is the link where you can download

 

[mabderezai]

gm-id design methodology

Hi All,
I took the ee240 class at Berkeley, and the truth is that the best way to learn is to go through the pain of doing the posted homeworks and look at the solutions... but in a nut shell here is what is fuss is all about.

1) B-sim level models are far from your first or second order approximation hand calculations. So, why do hand calculations?! have the simulator do a bunch of calculations for you, and then graph them, then you just look at the graph and see where you want to be.

2) Ok, what graph? you make these plots... gm/Id Vs Vgs, ro Vs Length (pick typical Widths) Id Vs Vg for a series of Lengths (pick a typical Width again) , all for a simple common source transistor configured in a circuit like one that I will post soon. (slide 30 of **broken link removed**)

3) to extract these parameters you can use Hspice parameter list, i.e:
.print dc +
myGmOverId = '(M1(LX7)/M1(L5)'

or something to that effect... I don't remember...

or you can run a bunch of .op and lookup the parameters (gm, ro, Id ...) and graph them in excel *perl would be handy*

4) now you have all your data... you can setup what L gives you gmro that you want... if that meets bandwidth you reduce your gm/id and find a new Vgs that maps to a whole new set of L and W, ... this post is not intended to cover gm/id (aka V*) methodology in one shot...

I hope at least this would motivate more designers to respond and ask questions... Once you learn how to design with this method, you can optimize better, faster, and save yourself pain... if you want to design in the 90nm and bellow, you won't be able to do so without the above method... of course then chances are you already know this method if your given the task of designing in 90nm... but for the rest of you stuck in .3 micron world and above... you can also use this and save yourself the pain of velocity saturation and a bunch of other crap that only physicist and process engineers care about, and focus on Gain Bandwidth and other nice circuity stuff... because the quantum effects are all in SPICE ... so use it as a lookup table...

Hope this helps/wasn't too long an confusing.